Using TMS320C6678 Processor to Implement Power Efficient Scalable H.265/HEVC Solution Ref Design
TIDEP0037
This product has been released to the market and is available for purchase. For some products, newer alternatives may be available.
This product has been released to the market and is available for purchase. For some products, newer alternatives may be available.
See the Important Notice and Disclaimer covering reference designs and other TI resources.
Key Document
- Using TMS320C6678 to Implement H.265/HEVC Design Guide (Rev. A)
(PDF 427 KB)
19 Oct 2015
Description
HEVC is an efficient, but processing intensive video standard, that is said to double the data compression ratio compared to H.264 / MPEG-4 at the same level of video quality. This design shows how a power efficient, soft H.265 / HEVC solution, that scales across resolutions, frame rates & profiles, can be implemented in real time using one or more TMS320C6678 devices. A specific use case of a single channel HEVC 720p30 real time encoder and single channel HEVC 1080p60 real time decoder is also included. TI’s HEVC C66x HEVC encoder shows a bitrate saving, for the same visual quality, of greater than 40% compared with TI’s H.264 x encoder. TMS320C66x DSPs support both audio and video codecs.
Features
- The TIDEP0037 reference design is tested, and includes a hardware reference (EVM), software and a user's guide.
- TMDSEVM6678 EVM for a high performance, cost-efficient, standalone development platform, using the TMS320C6678 high-performance DSP based on TI's C66x Keystone multicore architecture.
- This design includes schematics, design files, and a bill of materials.
- HEVC/ H.265 encoder and decoder, MCSDK framework and other software packages
- Design guide discusses performance and scalability across DSP cores and devices to achieve desired HEVC configuration
See the Important Notice and Disclaimer covering reference designs and other TI resources.
