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TMS320C6674

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High performance quad-core C66x fixed and floating-point DSP- up to 1.25GHz

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Data sheet

TMS320C6674

ACTIVE
Data sheet Order now

Product details

CPU 32-/64-bit Frequency (MHz) 1000, 1250 PCIe 2 PCIe Gen2 Hardware accelerators 0 Operating system DSP/BIOS Security Cryptographic acceleration Rating Catalog Operating temperature range (°C) -40 to 100
CPU 32-/64-bit Frequency (MHz) 1000, 1250 PCIe 2 PCIe Gen2 Hardware accelerators 0 Operating system DSP/BIOS Security Cryptographic acceleration Rating Catalog Operating temperature range (°C) -40 to 100
FCBGA (CYP) 841 576 mm² (24 mm × 24 mm)
  • Four TMS320C66x DSP Core Subsystems at 1.00 GHz and 1.25GHz
    • 160 GMAC/80 GFLOP @ 1.25GHz
    • 32KB L1P, 32KB L1D, 512KB L2 Per Core
    • 4MB Shared L2
  • Multicore Navigator and TeraNet Switch Fabric - 2 Tb
  • Network Coprocessors- Packet Accelerator, Security Accelerator
  • Four Lanes of SRIO 2.1 - 5 Gbaud Per Lane Full Duplex
  • Two Lanes PCIe Gen2 - 5 Gbaud Per Lane Full Duplex
  • HyperLink - 50Gbaud Operation, Full Duplex
  • Ethernet MAC Subsystem - Two SGMII Ports w/ 10/100/1000 Mbps operation
  • 64-Bit DDR3 Interface (DDR3-1600) - 8 GByte Addressable Memory Space
  • 16-Bit EMIF - Async SRAM, NAND and NOR Flash Support
  • Two Telecom Serial Ports (TSIP) - 2/4/8 Lanes at 32.768/16.384/8.192
  • UART Interface
  • I2C Interface
  • 16 GPIO Pins
  • SPI Interface
  • Sixteen 64-Bit Timers
  • Three On-Chip PLLs
  • Four TMS320C66x DSP Core Subsystems at 1.00 GHz and 1.25GHz
    • 160 GMAC/80 GFLOP @ 1.25GHz
    • 32KB L1P, 32KB L1D, 512KB L2 Per Core
    • 4MB Shared L2
  • Multicore Navigator and TeraNet Switch Fabric - 2 Tb
  • Network Coprocessors- Packet Accelerator, Security Accelerator
  • Four Lanes of SRIO 2.1 - 5 Gbaud Per Lane Full Duplex
  • Two Lanes PCIe Gen2 - 5 Gbaud Per Lane Full Duplex
  • HyperLink - 50Gbaud Operation, Full Duplex
  • Ethernet MAC Subsystem - Two SGMII Ports w/ 10/100/1000 Mbps operation
  • 64-Bit DDR3 Interface (DDR3-1600) - 8 GByte Addressable Memory Space
  • 16-Bit EMIF - Async SRAM, NAND and NOR Flash Support
  • Two Telecom Serial Ports (TSIP) - 2/4/8 Lanes at 32.768/16.384/8.192
  • UART Interface
  • I2C Interface
  • 16 GPIO Pins
  • SPI Interface
  • Sixteen 64-Bit Timers
  • Three On-Chip PLLs

The TMS320C6674 Multicore Fixed and Floating Point Digital Signal Processor is based on TI's KeyStone multicore architecture. Integrated with four C66x CorePac DSPs, each core runs at 1.0 to 1.25 GHz enabling up to 5 GHz. The device supports high-performance signal processing applications such as mission critical, medical imaging, test, and automation. The C6674 platform is power efficient and easy to use. The C66x CorePac DSP is fully backward compatible with all existing C6000 family of fixed and floating point DSPs.

The TMS320C6674 Multicore Fixed and Floating Point Digital Signal Processor is based on TI's KeyStone multicore architecture. Integrated with four C66x CorePac DSPs, each core runs at 1.0 to 1.25 GHz enabling up to 5 GHz. The device supports high-performance signal processing applications such as mission critical, medical imaging, test, and automation. The C6674 platform is power efficient and easy to use. The C66x CorePac DSP is fully backward compatible with all existing C6000 family of fixed and floating point DSPs.

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Top documentation Type Title Format options Date
* Data sheet TMS320C6674 Multicore Fixed and Floating-Point Digital Signal Processor datasheet (Rev. E) May 7, 2014
* Errata TMS320C6674 Multicore Fixed & Floating-Point DSP Silicon Errata (Revs 1.0, 2.0) (Rev. H) Jun 29, 2015
Application note DDR3 Design Requirements for KeyStone Devices (Rev. D) PDF | HTML Jul 7, 2022
Application note Keystone Error Detection and Correction EDC ECC (Rev. A) Jun 25, 2021
Application note How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A) PDF | HTML May 19, 2021
User guide SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V) Jun 1, 2020
Application note Using DSPLIB FFT Implementation for Real Input and Without Data Scaling PDF | HTML Jun 11, 2019
Application note Keystone Bootloader Resources and FAQ May 29, 2019
Application note Keystone Multicore Device Family Schematic Checklist PDF | HTML May 17, 2019
Application note Hardware Design Guide for KeyStone Devices (Rev. D) PDF | HTML Mar 21, 2019
Application note KeyStone I DDR3 interface bring-up PDF | HTML Mar 6, 2019
White paper Designing professional audio mixers for every scenario Jun 28, 2018
Application note Thermal Design Guide for DSP and Arm Application Processors (Rev. B) Aug 14, 2017
User guide Phase-Locked Loop (PLL) for KeyStone Devices User's Guide (Rev. I) Jul 26, 2017
Application note KeyStone I DDR3 Initialization (Rev. E) Oct 28, 2016
Application note SERDES Link Commissioning on KeyStone I and II Devices Apr 13, 2016
White paper Multicore SoCs stay a step ahead of SoC FPGAs Feb 23, 2016
Application note TI DSP Benchmarking PDF | HTML Jan 13, 2016
User guide Enhanced Direct memory Access 3 (EDMA3) for KeyStone Devices User's Guide (Rev. B) PDF | HTML May 6, 2015
User guide Multicore Navigator (CPPI) for KeyStone Architecture User's Guide (Rev. H) PDF | HTML Apr 9, 2015
White paper TI’s processors leading the way in embedded analytics Mar 3, 2015
User guide DDR3 Memory Controller for KeyStone I Devices User's Guide (Rev. E) Jan 20, 2015
Application note TI Keystone DSP PCIe SerDes IBIS-AMI Models Oct 9, 2014
Application note TI Keystone DSP Hyperlink SerDes IBIS-AMI Models Oct 9, 2014
User guide Power Sleep Controller (PSC) for KeyStone Devices User's Guide (Rev. C) Sep 4, 2014
User guide Serial RapidIO (SRIO) for KeyStone Devices User's Guide (Rev. C) Sep 3, 2014
More literature KeyStone Lab Manual - Training Jun 5, 2014
User guide System Analyzer User's Guide (Rev. F) Nov 18, 2013
User guide PCI Express (PCIe) for KeyStone Devices User's Guide (Rev. D) Sep 30, 2013
User guide DSP Bootloader for KeyStone Architecture User's Guide (Rev. C) Jul 15, 2013
White paper Another Look at the Future of Medical Processing Jul 12, 2013
White paper Medical Software Development on Keystone Devices Jul 12, 2013
White paper Accelerating high-performance computing development with Desktop Linux SDK Jul 8, 2013
User guide Gigabit Ethernet Switch Subsystem for KeyStone Devices User's Guide (Rev. D) Jul 3, 2013
User guide Memory Protection Unit (MPU) for KeyStone Devices User's Guide (Rev. A) Jun 28, 2013
User guide C66x CorePac User's Guide (Rev. C) Jun 28, 2013
User guide HyperLink for KeyStone Devices User's Guide (Rev. C) May 28, 2013
User guide Security Accelerator (SA) for KeyStone Devices User's Guide (Rev. B) Feb 5, 2013
Product overview Multicore DSPs for High-Performance Video Coding Jan 22, 2013
Product overview OpenMP Programming for TMS320C66x Multicore DSPs (Rev. A) Nov 5, 2012
Application note SerDes Implementation Guidelines for KeyStone I Devices Oct 31, 2012
Product overview TMS320C66x high-performance multicore DSPs for video surveillance Sep 6, 2012
Application note Multicore Programming Guide (Rev. B) Aug 29, 2012
User guide TMS320C6000 Optimizing Compiler v 7.4 User's Guide (Rev. U) Aug 21, 2012
User guide TMS320C6000 Assembly Language Tools v 7.4 User's Guide (Rev. W) Aug 21, 2012
User guide Packet Accelerator (PA) for KeyStone Devices User's Guide (Rev. A) Jul 11, 2012
White paper Leveraging multicore processors for machine vision applications May 9, 2012
User guide Semaphore2 Hardware Module for KeyStone Devices User's Guide (Rev. A) Apr 24, 2012
User guide Serial Peripheral Interface (SPI) for KeyStone Devices User’s Guide (Rev. A) Mar 30, 2012
User guide Chip Interrupt Controller (CIC) for KeyStone Devices User's Guide (Rev. A) Mar 27, 2012
User guide 64-Bit Timer (Timer64) for KeyStone Devices User's Guide (Rev. A) Mar 22, 2012
White paper Maximizing Multicore Efficiency with Navigator Runtime Feb 23, 2012
Application note PCIe Use Cases for KeyStone Devices Dec 13, 2011
User guide Multicore Shared Memory Controller (MSMC) for KeyStone Devices User's Guide (Rev. A) Oct 15, 2011
Application note Introduction to TMS320C6000 DSP Optimization Oct 6, 2011
User guide Debug and Trace for KeyStone I Devices User's Guide (Rev. A) Sep 22, 2011
User guide Inter-Integrated Circuit (I2C) for KeyStone Devices User's Guide Sep 2, 2011
White paper KeyStone Multicore SoC Tool Suite: one platform for all needs Jun 17, 2011
User guide External Memory Interface (EMIF16) for KeyStone Devices User's Guide (Rev. A) May 24, 2011
White paper Software and Hardware Design Challenges Due to Dynamic Raw NAND Market May 19, 2011
Product overview TMS320C6671/72/74/78 High-Performance Multicore Fixed- and Floating-Point DSPs (Rev. B) Apr 25, 2011
Application note TMS320C66x DSP Generation of Devices (Rev. A) Apr 25, 2011
White paper KeyStone Memory Architecture White Paper (Rev. A) Dec 21, 2010
Application note Optimizing Loops on the C66x DSP Nov 9, 2010
User guide General-Purpose Input/Output (GPIO) forKeyStone Devices User's Guide Nov 9, 2010
User guide C66x CPU and Instruction Set Reference Guide Nov 9, 2010
Application note Clocking Design Guide for KeyStone Devices Nov 9, 2010
User guide Universal Asynchronous Receiver/Transmitter (UART) for KeyStone Devices UG Nov 9, 2010
User guide C66x DSP Cache User's Guide Nov 9, 2010
User guide Telecom Serial Interface Port (TSIP) for KeyStone Devices User's Guide Nov 9, 2010
User guide Network Coprocessor for KeyStone Devices User's Guide Nov 2, 2010

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