TIDA-00153
使用高速 ADC 的 JESD204B 連結延遲設計
TIDA-00153
概覽
JESD204B links are the latest trend in data-converter digital interfaces. These links take advantage of high-speed serial-digital technology to offer many compelling benefits including improved channel densities. This reference design addresses one of the challenges of adopting the new interface: understanding and designing the link latency. An example achieves deterministic latency and determines the link latency of a system containing the Texas Instruments LM97937 ADC and Xilinx Kintex 7 FPGA.
特點
- Guarantee deterministic latency across the JESD204B link
- Understand the tradeoff between link latency and tolerance to link delay variation
- Use a formulaic and procedure-based approach to design the link latency
- Implement a JESD204B link using Texas Instruments' ADC16DX370 or LM97937 ADC and a Xilinx Kintex 7 FPGA
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檢視所有 2
| 類型 | 標題 | 下載最新的英文版本 | 日期 | |||
|---|---|---|---|---|---|---|
| * | 設計指南 | JESD204B Link Latency Using a High-Speed ADC and FPGA Design Guide | 2014/2/18 | |||
| * | 測試報告 | TIDA-00153 Test Results | 2014/2/19 |