SNAS468D Data sheet

SNAS468D September 2008 – December 2014 ADC161S626

PRODUCTION DATA.

Package Options

Mechanical Data (Package|Pins)

DGS|10
- MPDS035C

Thermal pad, mechanical data (Package|Pins)

Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾⁽³⁾⁽²⁾

	MIN	MAX	UNIT
Analog Supply Voltage V_A	−0.3	6.5	V
Digital I/O Supply Voltage V_IO	−0.3	6.5	V
Voltage on Any Analog Input Pin to GND	−0.3	(V_A + 0.3)	V
Voltage on Any Digital Input Pin to GND	−0.3	(V_IO + 0.3)	V
Input Current at Any Pin⁽⁴⁾	–10	10	mA
Package Input Current⁽⁴⁾	–50	50	mA
Power Consumption at T_A = 25°C		See ⁽⁵⁾
Junction Temperature		150	°C
Storage temperature, T_stg	−65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.

(3) All voltages are measured with respect to GND = 0 V, unless otherwise specified.

(4) When the input voltage at any pin exceeds the power supplies (that is, V_IN < GND or V_IN > V_A), the current at that pin should be limited to 10 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to five.

(5) The absolute maximum junction temperature (T_Jmax) for this device is 150°C. The maximum allowable power dissipation is dictated by T_Jmax, the junction-to-ambient thermal resistance (θ_JA), and the ambient temperature (T_A), and can be calculated using the formula P_DMAX = (T_Jmax − T_A)/θ_JA. The values for maximum power dissipation listed above will be reached only when the ADC161S626 is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Such conditions should always be avoided.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2500	V
		Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1250
		Machine model (MM)	250

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

	MIN	MAX	UNIT
Operating Temperature Range	−40	85	°C
Supply Voltage, V_A	4.5	5.5	V
Supply Voltage, V_IO	2.7	5.5	V
Reference Voltage, V_REF	0.5	V_A	V
Analog Input Pins Voltage Range	0	V_A	V
Differential Analog Input Voltage	−V_REF	+V_REF	V
Input Common-Mode Voltage, V_CM		See Figure 44
Digital Input Pins Voltage Range	0	V_IO	V
Clock Frequency	1	5	MHz

(1) All voltages are measured with respect to GND = 0V, unless otherwise specified.

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		ADC161S626	UNIT
		DGS
		10 PINS
R_θJA	Junction-to-ambient thermal resistance	163	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	57
R_θJB	Junction-to-board thermal resistance	82
ψ_JT	Junction-to-top characterization parameter	6
ψ_JB	Junction-to-board characterization parameter	81

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Converter Electrical Characteristics

The following specifications apply for V_A = 4.5 V to 5.5 V, V_IO = 2.7 V to 5.5 V, and V_REF = 2.5 V to 5.5 V for f_SCLK = 1 MHz to 4 MHz or V_REF = 4.5 V to 5.5 V for f_SCLK = 1 MHz to 5 MHz; f_IN = 20 kHz, and C_L = 25 pF, unless otherwise noted. Maximum and minimum values apply for T_A = T_MIN to T_MAX; the typical values are tested at T_A = 25°C.⁽¹⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
STATIC CONVERTER CHARACTERISTICS
	Resolution with No Missing Codes				16	Bits
DNL	Differential Non-Linearity		−1	-0.5/+0.8	+2	LSB
INL	Integral Non-Linearity		−2	±0.8	+2	LSB
OE	Offset Error	V_REF = 2.5 V	−1	−0.1	+1	mV
OE	Offset Error	V_REF = 5 V		−0.4		mV
OE_DRIFT	Offset Error Temperature Drift	V_REF = 2.5 V		3.7		µV/°C
OE_DRIFT	Offset Error Temperature Drift	V_REF = 5 V		2.5		µV/°C
FSE	Positive Full-Scale Error		–0.03	−0.003	0.03	%FS
FSE	Negative Full-Scale Error		–0.03	−0.002	0.03	%FS
GE	Positive Gain Error		–0.02	−0.002	0.02	%FS
GE	Negative Gain Error		–0.02	−0.0001	0.02	%FS
GE_DRIFT	Gain Error Temperature Drift			0.3		ppm/°C
DYNAMIC CONVERTER CHARACTERISTICS
SINAD	Signal-to-Noise Plus Distortion Ratio	V_REF = 2.5 V	85	88		dBc
SINAD	Signal-to-Noise Plus Distortion Ratio	V_REF = 4.5 V to 5.5 V	89	93.0		dBc
SNR	Signal-to-Noise Ratio	V_REF = 2.5 V	85	88		dBc
SNR	Signal-to-Noise Ratio	V_REF = 4.5 V to 5.5 V	89	93.2		dBc
THD	Total Harmonic Distortion	V_REF = 2.5 V		−104		dBc
THD	Total Harmonic Distortion	V_REF = 4.5 V to 5.5 V		−106		dBc
SFDR	Spurious-Free Dynamic Range	V_REF = 2.5 V		108		dBc
SFDR	Spurious-Free Dynamic Range	V_REF = 4.5 V to 5.5 V		111		dBc
ENOB	Effective Number of Bits	V_REF = 2.5 V	13.8	14.3		bits
ENOB	Effective Number of Bits	V_REF = 4.5 V to 5.5 V	14.5	15.2		bits
FPBW	−3 dB Full Power Bandwidth	Output at 70.7%FS with FS Differential Input		26		MHz
ANALOG INPUT CHARACTERISTICS
V_IN	Differential Input Range		−V_REF		+V_REF	V
I_INA	Analog Input Current	CS high	–1		1	µA
		V_REF = 5 V, V_IN = 0 V, f_S = 50 kSPS		3.2		nA
		V_REF = 5 V, V_IN = 0 V, f_S = 200 kSPS		10.3		nA
C_INA	Input Capacitance (+IN or −IN)	In Acquisition Mode		20		pF
C_INA	Input Capacitance (+IN or −IN)	In Conversion Mode		4		pF
CMRR	Common Mode Rejection Ratio	See the Specification Definitions for the test condition		85		dB
DIGITAL INPUT CHARACTERISTICS
V_IH	Input High Voltage	f_IN = 0 Hz	0.7 x V_IO	1.9		V
V_IL	Input Low Voltage	f_IN = 0 Hz		1.7	0.3 x V_IO	V
I_IND	Digital Input Current		–1		1	µA
C_IND	Input Capacitance				4	pF
DIGITAL OUTPUT CHARACTERISTICS
V_OH	Output High Voltage	I_SOURCE = 200 µA	V_IO − 0.2	V_IO − 0.03		V
V_OH	Output High Voltage	I_SOURCE = 1 mA		V_IO − 0.09		V
V_OL	Output Low Voltage	I_SOURCE = 200 µA		0.01	0.4	V
V_OL	Output Low Voltage	I_SOURCE = 1 mA		0.07		V
I_OZH, I_OZL	TRI-STATE Leakage Current	Force 0V or V_A	–1		1	µA
C_OUT	TRI-STATE Output Capacitance	Force 0V or V_A		4		pF
	Output Coding		Binary 2's Complement
POWER SUPPLY CHARACTERISTICS
V_A	Analog Supply Voltage Range		4.5	5	5.5	V
V_IO	Digital Input/Output Supply Voltage Range	⁽²⁾	2.7	3	5.5	V
V_REF	Reference Voltage Range		0.5	5	V_A	V
I_VA (Conv)	Analog Supply Current, Conversion Mode	V_A = 5 V, f_SCLK = 4 MHz, f_S = 200 kSPS		1060		µA
I_VA (Conv)	Analog Supply Current, Conversion Mode	V_A = 5 V, f_SCLK = 5 MHz, f_S = 250 kSPS		1160	1340	µA
I_VIO (Conv)	Digital I/O Supply Current, Conversion Mode	V_IO = 3 V, f_SCLK = 4 MHz, f_S = 200 kSPS		80		µA
I_VIO (Conv)	Digital I/O Supply Current, Conversion Mode	V_IO = 3 V, f_SCLK = 5 MHz, f_S = 250 kSPS		100		µA
I_VREF (Conv)	Reference Current, Conversion Mode	V_A = 5 V, f_SCLK = 4 MHz, f_S = 200 kSPS		80		µA
I_VREF (Conv)	Reference Current, Conversion Mode	V_A = 5 V, f_SCLK = 5 MHz, f_S = 250 kSPS		100	170	µA
I_VA (PD)	Analog Supply Current, Power Down Mode (CS high)	f_SCLK = 5 MHz, V_A = 5 V		7		µA
I_VA (PD)	Analog Supply Current, Power Down Mode (CS high)	f_SCLK = 0 Hz, V_A = 5 V⁽³⁾		2	3	µA
I_VIO (PD)	Digital I/O Supply Current, Power Down Mode (CS high)	f_SCLK = 5 MHz, V_IO = 3 V		1		µA
I_VIO (PD)	Digital I/O Supply Current, Power Down Mode (CS high)	f_SCLK = 0 Hz, V_IO = 3 V⁽³⁾		0.3	0.5	µA
I_VREF (PD)	Reference Current, Power Down Mode (CS high)	f_SCLK = 5 MHz, V_REF = 5 V		0.5		µA
I_VREF (PD)	Reference Current, Power Down Mode (CS high)	f_SCLK = 0 Hz, V_REF = 5 V⁽³⁾		0.5	0.7	µA
PWR (Conv)	Power Consumption, Conversion Mode	V_A = 5 V, f_SCLK = 4 MHz, f_S = 200 kSPS, and f_IN = 20 kHz,		5.3		mW
PWR (Conv)	Power Consumption, Conversion Mode	V_A = 5 V, f_SCLK = 5 MHz, f_S = 250 kSPS, and f_IN = 20		5.8	6.7	mW
PWR (PD)	Power Consumption, Power Down Mode (CS high)	f_SCLK = 5 MHz, V_A = 5.0 V⁽³⁾		35		µW
PWR (PD)	Power Consumption, Power Down Mode (CS high)	f_SCLK = 0 Hz, V_A = 5.0 V⁽³⁾		10	15	µW
PSRR	Power Supply Rejection Ratio	See the Specification Definitions for the test condition		−78		dB
AC ELECTRICAL CHARACTERISTICS
f_SCLK	Maximum Clock Frequency		1		5	MHz
f_S	Maximum Sample Rate	⁽⁴⁾	50		250	kSPS
t_ACQ	Acquisition/Track Time		600			ns
t_CONV	Conversion/Hold Time				17	SCLK cycles
t_AD	Aperture Delay	See the Specification Definitions		6		ns

(1) Typical values are at T_J = 25°C and represent most likely parametric norms. Test limits are specified to AOQL (Average Outgoing Quality Level).

(2) The value of V_IO is independent of the value of V_A. For example, V_IO could be operating at 5.5 V while V_A is operating at 4.5V or V_IO could be operating at 2.7 V while V_A is operating at 5.5 V.

(3) This parameter is ensured by design and/or characterization and is not tested in production.

(4) While the maximum sample rate is f_SCLK / 20, the actual sample rate may be lower than this by having the CS rate slower than f_SCLK / 20.

6.6 Timing Requirements

The following specifications apply for V_A = 4.5 V to 5.5 V, V_IO = 2.7 V to 5.5 V, V_REF = 2.5 V to 5.5 V, f_SCLK = 1Mz to 5MHz, and C_L = 25 pF, unless otherwise noted. Maximum and minimum values apply for T_A = T_MIN to T_MAX; the typical values are tested at T_A = 25°C.⁽¹⁾

		MIN	NOM	MAX	UNIT
t_CSS	CS Setup Time prior to an SCLK rising edge	8	3		ns
t_CSH	CS Hold Time after an SCLK rising edge	8	3
t_DH	D_OUT Hold Time after an SCLK falling edge	6	11		ns
t_DA	D_OUT Access Time after an SCLK falling edge		18	41	ns
t_DIS	D_OUT Disable Time after the rising edge of CS⁽²⁾		20	30	ns
t_CS	Minimum CS Pulse Width	20			ns
t_EN	D_OUT Enable Time after the 2nd falling edge of SCLK		20	70	ns
t_CH	SCLK High Time	20			ns
t_CL	SCLK Low Time	20			ns
t_r	D_OUT Rise Time		7		ns
t_f	D_OUT Fall Time		7		ns