SPRSPA3A March 2024 – September 2024 AM67 , AM67A
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
Table 6-105, Figure 6-77, Table 6-106, and Figure 6-78 present timing requirements and switching characteristics for MMC1/MMC2 – UHS-I SDR12 Mode.
NO. | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
SDR121 | tsu(cmdV-clkH) | Setup time, MMCx_CMD valid before MMCx_CLK rising edge | 4.2 | ns | |
SDR122 | th(clkH-cmdV) | Hold time, MMCx_CMD valid after MMCx_CLK rising edge | 0.87 | ns | |
SDR123 | tsu(dV-clkH) | Setup time, MMCx_DAT[3:0] valid before MMCx_CLK rising edge | 4.2 | ns | |
SDR124 | th(clkH-dV) | Hold time, MMCx_DAT[3:0] valid after MMCx_CLK rising edge | 0.87 | ns |
NO. | PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|---|
fop(clk) | Operating frequency, MMCx_CLK | 25 | MHz | ||
SDR125 | tc(clk) | Cycle time, MMCx_CLK | 40 | ns | |
SDR126 | tw(clkH) | Pulse duration, MMCx_CLK high | 18.7 | ns | |
SDR127 | tw(clkL) | Pulse duration, MMCx_CLK low | 18.7 | ns | |
SDR128 | td(clkL-cmdV) | Delay time, MMCx_CLK rising edge to MMCx_CMD transition | 1.5 | 8.6 | ns |
SDR129 | td(clkL-dV) | Delay time, MMCx_CLK rising edge to MMCx_DAT[3:0] transition | 1.5 | 8.6 | ns |