SPRSPA3A March 2024 – September 2024 AM67 , AM67A
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
Table 6-101, Figure 6-84, Table 6-102, and Figure 6-85 present timing requirements and switching characteristics for MMC1/MMC2 – Default Speed Mode.
NO. | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
DS1 | tsu(cmdV-clkH) | Setup time, MMCx_CMD valid before MMCx_CLK rising edge | 2.15 | ns | |
DS2 | th(clkH-cmdV) | Hold time, MMCx_CMD valid after MMCx_CLK rising edge | 1.67 | ns | |
DS3 | tsu(dV-clkH) | Setup time, MMCx_DAT[3:0] valid before MMCx_CLK rising edge | 2.15 | ns | |
DS4 | th(clkH-dV) | Hold time, MMCx_DAT[3:0] valid after MMCx_CLK rising edge | 1.67 | ns |
NO. | PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|---|
fop(clk) | Operating frequency, MMCx_CLK | 25 | MHz | ||
DS5 | tc(clk) | Cycle time, MMCx_CLK | 40 | ns | |
DS6 | tw(clkH) | Pulse duration, MMCx_CLK high | 18.7 | ns | |
DS7 | tw(clkL) | Pulse duration, MMCx_CLK low | 18.7 | ns | |
DS8 | td(clkL-cmdV) | Delay time, MMCx_CLK falling edge to MMCx_CMD transition | - 1.8 | 2.2 | ns |
DS9 | td(clkL-dV) | Delay time, MMCx_CLK falling edge to MMCx_DAT[3:0] transition | - 1.8 | 2.2 | ns |