SBAS422B July   2007  – January 2018 DAC8881

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Block Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Characteristics for
    7. 6.7 Timing Characteristics for and
    8. 6.8 Typical Characteristics: VDD = +5 V
    9. 6.9 TYpical Characteristics: VDD = +2.7 V
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Output
      2. 7.3.2  Reference Inputs
      3. 7.3.3  Output Range
      4. 7.3.4  Input Data Format
      5. 7.3.5  Hardware Reset
      6. 7.3.6  Power-On Reset
      7. 7.3.7  Program Reset Value
      8. 7.3.8  Power Down
      9. 7.3.9  Double-Buffered Interface
      10. 7.3.10 Load DAC Pin (LDAC)
        1. 7.3.10.1 Synchronous Mode
        2. 7.3.10.2 Asynchronous Mode
      11. 7.3.11 1.8 V to 5.5 V Logic Interface
    4. 7.4 Device Functional Modes
      1. 7.4.1 Serial Interface
        1. 7.4.1.1 Input Shift Register
          1. 7.4.1.1.1 Stand-Alone Mode
          2. 7.4.1.1.2 Daisy-Chain Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Bipolar Operation Using The DAC8881
    2. 8.2 Typical Application
      1. 8.2.1 DAC8881 Sample Hold Circuit
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 System Example
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

RGE Package1
QFN-24
(Top View)
DAC8881 po_bas422.gif
1. The thermal pad is internally connected to the substrate. This pad can be connected to the analog ground or left floating. Keep the thermal pad separate from the digital ground, if possible.

Pin Functions

PINI/ODESCRIPTION
NO.NAME
1 SCLK I SPI bus serial clock input
2 SDI I SPI bus serial data input
3 LDAC I Load DAC latch control input (active low). When LDAC is low, the DAC latch is transparent, and the contents of the input register are transferred to the DAC latch. The DAC output changes to the corresponding level simultaneously when the DAC latch is updated.
4 AGND I Analog ground
5 AVDD I Analog power supply
6 VREFL-S I Reference low input sense
7 VREFH-S I Reference high input sense
8 VOUT O Output of output buffer
9 RFB I Feedback resistor connected to the inverting input of the output buffer.
10 VREFL-F I Reference low input force
11 VREFH-F I Reference high input force
12 NC — Do not connect.
13 NC — Do not connect.
14 RSTSEL I Selects the value of the output from the VOUT pin after power-on or hardware reset. If RSTSEL = IOVDD, then register data = 8000h. If RSTSEL = DGND, then register data = 0000h.
15 GAIN I Buffer gain setting. Gain = 1 when the pin is connected to DGND; Gain = 2 when the pin is connected to IOVDD.
16 USB/BTC I Input data format selection. Input data are straight binary format when the pin is connected to IOVDD, and in two’s complement format when the pin is connected to DGND.
17 RST I Reset input (active low). Logic low on this pin causes the device to perform a reset.
18 PDN I Power-down input (active high). Logic high on this pin forces the device into power-down status. In power-down, the VOUT pin connects to AGND through 10kΩ resistor.
19 CS I SPI bus chip select input (active low). Data bits are not clocked into the serial shift register unless CS is low. When CS is high, SDO is in high-impedance status.
20 SDOSEL I SPI serial data output selection. When SDOSEL is tied to IOVDD, the contents of the existing input register are shifted out from the SDO pin; this is Stand-Alone mode. When SDOSEL is tied to DGND, the contents in the SPI input shift register are shifted out from the SDO pin; this is Daisy-Chain mode for daisy chaining communication.
21 DVDD I Digital power supply (connect to AVDD, pin 5)
22 DGND I Digital ground
23 SDO O SPI bus serial data output. Refer to the Timing Diagrams for further detail.
24 IOVDD I Interface power. Connect to +1.8V for 1.8V logic, +3V for 3V logic, and to +5V for 5V logic.