SNLS683 june   2023 DS320PR1601

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD and Latchup Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Characteristics
    8. 6.8 Typical Characteristics
    9. 6.9 Typical Jitter Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Linear Equalization
      2. 7.3.2 Flat-Gain
      3. 7.3.3 Receiver Detect State Machine
      4. 7.3.4 Five-Level Control Inputs
      5. 7.3.5 Integrated Capacitors
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active PCIe Mode
      2. 7.4.2 Active Buffer Mode
      3. 7.4.3 Standby Mode
  9. 8 Programming
    1. 8.1 Pin Configurations for Lanes
    2. 8.2 SMBUS/I2C Register Control Interface
      1. 8.2.1 Shared Registers
      2. 8.2.2 Channel Registers
    3. 8.3 SMBus/I 2 C Controller Mode Configuration (EEPROM Self Load)
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 PCIe x16 Lane Configuration
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.1 Linear Equalization

The DS320PR1601 receivers feature a continuous-time linear equalizer (CTLE) that applies high-frequency boost and low-frequency attenuation to help equalize the frequency-dependent insertion loss effects of the passive channel. The device has 18 available equalization boost settings that can be set though SMBus/I2C registers. Table 7-1 provides the device EQ settings.

Refer to the DS160PR1601 and DS320PR1601 Programming Guide for detail register sets and control configuration procedures.
Table 7-1 Equalization Control Settings
EQUALIZATION SETTING TYPICAL EQ BOOST (dB)
EQ INDEX at 4 GHz at 8 GHz at 16 GHz
0 1.5 2.9 2.9
1 2.1 4.3 4.9
2 2.8 5.7 6.9
5 3.7 6.4 9.2
6 4.1 7.2 10.1
7 4.4 7.8 10.9
8 4.9 8.5 11.5
9 5.3 9.1 12.2
10 5.9 10.1 13.5
11 6.2 10.5 14.0
12 6.9 11.5 15.0
13 7.5 12.4 15.8
14 7.7 12.7 16.5
15 8.1 13.5 17.5
16 8.4 14.1 18.3
17 8.9 14.9 19.2
18 9.3 15.6 20.0
19 9.8 16.3 21.0

Note in I2C mode default EQ setting does not map one of the EQ index, as provided in Table 7-1. EQ Boost values are same as EQ INDEX = 5 with slightly different EQ profile.

EQ profile selection option available through I2C shared register 0x03 provides subtle EQ gain curve modification option to match board trace or cable loss profile. The fine tuning alters mid frequency EQ boost values. EQ profile controls are thermometer coded and increase boost at 1 GHz by about 0.5 dB per setting increase. The equalization boost values for the range of 4-16 GHz are mostly unchanged with this subtle EQ gain profile change.