SNLS683 june   2023 DS320PR1601

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD and Latchup Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Characteristics
    8. 6.8 Typical Characteristics
    9. 6.9 Typical Jitter Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Linear Equalization
      2. 7.3.2 Flat-Gain
      3. 7.3.3 Receiver Detect State Machine
      4. 7.3.4 Five-Level Control Inputs
      5. 7.3.5 Integrated Capacitors
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active PCIe Mode
      2. 7.4.2 Active Buffer Mode
      3. 7.4.3 Standby Mode
  9. 8 Programming
    1. 8.1 Pin Configurations for Lanes
    2. 8.2 SMBUS/I2C Register Control Interface
      1. 8.2.1 Shared Registers
      2. 8.2.2 Channel Registers
    3. 8.3 SMBus/I 2 C Controller Mode Configuration (EEPROM Self Load)
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 PCIe x16 Lane Configuration
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.1 Shared Registers

Table 8-3 General Registers (Offset = 0xE2)
Bit Field Type Reset Description
7 RESERVED R 0x0 Reserved
6 rst_i2c_regs R/W/SC 0x0 Device reset control: Reset all I2C registers to default values (self-clearing).
5 rst_i2c_mas R 0x0 Reserved
4-1 RESERVED R 0x0 Reserved
0 frc_eeprm_rd R/W/SC 0x0 Override MODE and READ_EN_N status to force manual EEPROM configuration load.
Table 8-4 DEVICE_ID0 Register (Offset = 0xF0)
Bit Field Type Reset Description
7-5 RESERVED R 0x0 Reserved
4 RESERVED R 0x1 Reserved
3 device_id0_3 R 0x0 Device ID0 [3:1]: 011
2 device_id0_2 R 0x1 see MSB
1 device_id0_1 R 0x1 see MSB
0 RESERVED R 0 Reserved
Table 8-5 DEVICE_ID1 Register (Offset = 0xF1)
Bit Field Type Reset Description
7 device_id[7] R 0x0 Device ID 0010 1001: DS320PR1601
6 device_id[6] R 0x0 see MSB
5 device_id[5] R 0x1 see MSB
4 device_id[4] R 0x0 see MSB
3 device_id[3] R 0x1 see MSB
2 device_id[2] R 0x0 see MSB
1 device_id[1] R 0x0 see MSB
0 device_id[0] R 0x1 see MSB