SNLS683 june   2023 DS320PR1601

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD and Latchup Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Characteristics
    8. 6.8 Typical Characteristics
    9. 6.9 Typical Jitter Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Linear Equalization
      2. 7.3.2 Flat-Gain
      3. 7.3.3 Receiver Detect State Machine
      4. 7.3.4 Five-Level Control Inputs
      5. 7.3.5 Integrated Capacitors
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active PCIe Mode
      2. 7.4.2 Active Buffer Mode
      3. 7.4.3 Standby Mode
  9. 8 Programming
    1. 8.1 Pin Configurations for Lanes
    2. 8.2 SMBUS/I2C Register Control Interface
      1. 8.2.1 Shared Registers
      2. 8.2.2 Channel Registers
    3. 8.3 SMBus/I 2 C Controller Mode Configuration (EEPROM Self Load)
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 PCIe x16 Lane Configuration
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The DS320PR1601 is a 32-channel (16-channel in each direction) or x16 (16-lane) low-power high-performance linear repeater or redriver designed to support PCIe 5.0, CXL 2.0, UPI 2.0 and other interfaces up to 32 Gbps.

The DS320PR1601 receivers deploy continuous time linear equalizers (CTLE) to provide a programmable high-frequency boost. The equalizer can open an input eye that is completely closed due to inter-symbol interference (ISI) induced by an interconnect medium, such as PCB traces. The CTLE receiver is followed by a linear output driver. The linear datapaths of DS320PR1601 preserves transmit preset signal characteristics. The linear redriver becomes part of the passive channel that as a whole get link trained for best transmit and receive equalization settings. This transparency in the link training protocol results in best electrical link and lowest possible latency. Low channel-channel cross-talk, low additive jitter and excellent return loss makes the device almost a passive element in the link, but with its equalization.

Package Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2)
DS320PR1601 ZDG (nfBGA, 354) 22.89 mm × 8.9 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
(2) The package size (length × width) is a nominal value and includes pins, where applicable..

GUID-20210928-SS0I-WKXP-T9P3-JXCWXPL0WCPZ-low.svg Typical Application