7.3.1 Data Transfer

The DS90UR907Q transmits a pixel of data in the following format: C1 and C0 represent the embedded clock in the serial stream. C1 is always HIGH and C0 is always LOW. b[23:0] contain the scrambled RGB data. DCB is the DC-Balanced control bit. DCB is used to minimize the short and long-term DC bias on the signal lines. This bit determines if the data is unmodified or inverted. DCA is used to validate data integrity in the embedded data stream and can also contain encoded control (VS,HS,DE). Both DCA and DCB coding schemes are generated by the DS90UR907Q and decoded by the paring deserializer automatically reference to FPD-Link II Serial Stream. Figure 14 illustrates the serial stream per PCLK cycle.

Figure 14. FPD-Link II Serial Stream

7.3.2 Operating Modes And Backward Compatibility - Config[1:0]

The DS90UR907Q is backward compatible with previous generations of FPD-Link II deserializers. Configuration modes are provided for backwards compatibility with the DS90C124 FPD-Link II Generation 1, and also the DS90UR124 FPD-Link II Generation 2 deserializers by setting the respective mode with the CONFIG[1:0] pins as shown in Table 1. The selection also determine whether the Video Control Signal filter feature is enabled or disabled in Normal mode.

7.3.3 Video Control Signal Filter

When operating the devices in Normal Mode, the Video Control Signals (DE, HS, VS) have the following restrictions:

• Normal Mode with Control Signal Filter Enabled:
  • DE and HS — Only 2 transitions per 130 clock cycles are transmitted, the transition pulse must be 3 PCLK or longer.
• Normal Mode with Control Signal Filter Disabled:
  • DE and HS — Only 2 transitions per 130 clock cycles are transmitted, no restriction on minimum transition pulse.
• VS — Only 1 transition per 130 clock cycles are transmitted, minimum pulse width is 130 clock cycles.

Video Control Signals are defined as low-frequency signals with limited transitions. Glitches of a control signal can cause a visual display error. This feature allows for the chipset to validate and filter out any high-frequency noise on the control signals. See Figure 15.

Figure 15. Video Control Signal Filter Waveform

7.3.4 Color Bit Mapping Select

The DS90UR907Q can be configured to accept 24-bit color (8-bit RGB) with 2 different mapping schemes: LSBs on RxIN[3] shown in Figure 16 or MSBs on RxIN[3] shown in Figure 17. The mapping scheme is controlled by MAPSEL pin or by Register.

Figure 16. 8–Bit FPD-Link Mapping: LSB's on Rxin3

Figure 17. 8–Bit FPD-Link Mapping: MSB's on Rxin3

7.3.5 EMI Reduction Features

7.3.6 Signal Quality Enhancers

7.3.6.2 De-Emphasis (De-Emph)

The De-Emph pin controls the amount of de-emphasis beginning one full bit time after a logic transition that the device drives. It is the signal conditioning function for use in compensating against cable transmission loss. This pin should be left open for standard switching currents (no de-emphasis) or if controlled by register. De-emphasis is selected by connecting a resistor on this pin to ground, with R value from 0.5 kΩ to 1 MΩ, or by register setting. When using De-Emphasis, TI recommends setting VODSEL = H.

Table 3. De-Emphasis Resistor Value

RESISTOR VALUE (kΩ)	DE-EMPHASIS SETTING
Open	Disabled
0.6	–12 dB
1	–9 dB
2	–6 dB
5	–3 dB

Figure 18. De-Emph vs R Value

7.3.7 Power Saving Features

7.4.1 Operating Modes and Backward Compatibility (Config[1:0])

The DS90UR907Q is backward compatible with previous generations of FPD-Link II deserializers. Configuration modes are provided for backwards compatibility with the DS90C124 FPD-LinkII Generation 1, and also the DS90UR124 FPD-Link II Generation 2 deserializers by setting the respective mode with the CONFIG[1:0] pins as shown in Table 4. The selection also determines whether the Video Control Signal filter feature is enabled or disabled in Normal mode.

7.5.1 Optional Serial Bus Control

See the following section on the Optional Serial Bus Control Interface.

7.5.2 Built In Self Test (BIST)

An optional At-Speed Built In Self Test (BIST) feature supports the testing of the high-speed serial link. This is useful in the prototype stage, equipment production, in-system test and also for system diagnostics. In the BIST mode only a input clock is required along with control to the DS90UR907Q and deserializer BISTEN input pins. The DS90UR907Q outputs a test pattern (PRBS7) and drives the link at speed. The deserializer detects the PRBS7 pattern and monitors it for errors. A PASS output pin toggles to flag any payloads that are received with 1 to 24 errors. Upon completion of the test, the result of the test is held on the PASS output until reset (new BIST test or Power Down). A high on PASS indicates NO ERRORS were detected. A Low on PASS indicates one or more errors were detected. The duration of the test is controlled by the pulse width applied to the deserializer BISTEN pin.

Inter-operability is supported between this FPD-Link II device and all FPD-Link II generations (Gen 1/2/3) — see respective data sheets for details on entering BIST mode and control.

Sample BIST Sequence

See Figure 19 for the BIST mode flow diagram.

Step 1: Place the DS90UR907Q in BIST Mode by setting Ser BISTEN = H. The BIST Mode is enabled through the BISTEN pin. An RxCLKIN is required for all the Ser options. When the deserializer detects the BIST mode pattern and command (DCA and DCB code) the RGB and control signal outputs are shut off.

Step 2: Place the pairing deserializer in BIST mode by setting the BISTEN = H. The Des is now in the BIST mode and checks the incoming serial payloads for errors. If an error in the payload (1 to 24) is detected, the PASS pin will switch low for one half of the clock period. During the BIST test, the PASS output can be monitored and counted to determine the payload error rate.

Step 3: To Stop the BIST mode, the deserializer BISTEN pin is set Low. The deserializer stops checking the data and the final test result is held on the PASS pin. If the test ran error free, the PASS output will be High. If there was one or more errors detected, the PASS output will be Low. The PASS output state is held until a new BIST is run, the device is RESET, or Powered Down. The BIST duration is user controlled by the duration of the BISTEN signal.

Step 4: To return the link to normal operation, the DS90UR907Q BISTEN input is set Low. The Link returns to normal operation.

Figure 20 shows the waveform diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2 shows one with multiple errors. In most cases it is difficult to generate errors due to the robustness of the link (differential data transmission and so forth), thus they may be introduced by greatly extending the cable length, faulting the interconnect, reducing signal condition enhancements (De-Emphasis, VODSEL, or deserializer Equalization).

Figure 19. BIST Mode Flow Diagram

BER Calculations

It is possible to calculate the approximate Bit Error Rate (BER). The following is required:

• Pixel Clock Frequency (MHz)
• BIST Duration (seconds)
• BIST test Result (PASS)

The BER is less than or equal to one over the product of 24 times the RxCLKIN rate times the test duration. If we assume a 65-MHz RxCLKIN, a 10 minute (600 second) test, and a PASS, the BERT is ≤ 1.07 × 10E-12

The BIST mode runs a check on the data payload bits. The LOCK pin also provides a link status. It the recovery of the C0 and C1 bits does not reconstruct the expected clock signal, the LOCK pin will switch Low. The combination of the LOCK and At-Speed BIST PASS pin provides a powerful tool for system evaluation and performance monitoring.

Figure 20. BIST Waveforms

7.5.3 Optional Serial Bus Control

The DS90UR907Q may be configured by the use of a serial control bus that is I²C protocol compatible. By default, the I²C reg_0x00'h is set to 00'h and all configuration is set by control/strap pins. A write of 01'h to reg_0x00'h will enable/allow configuration by registers; this will override the control/strap pins. Multiple devices may share the serial control bus because multiple addresses are supported. See Figure 21.

The serial bus is comprised of three pins. The SCL is a Serial Bus Clock Input. The SDA is the Serial Bus Data Input / Output signal. Both SCL and SDA signals require an external pullup resistor to V_DDIO. For most applications a 4.7-k pullup resistor to V_DDIO may be used. The resistor value may be adjusted for capacitive loading and data rate requirements. The signals are either pulled High, or driven Low.

Figure 21. Serial Control Bus Connection

The third pin is the ID[x] pin. This pin sets one of four possible device addresses. Two different connections are possible. The pin may be pulled to V_DD (1.8 V, NOT V_DDIO)) with a 10-kΩ resistor. Or a 10-kΩ pullup resistor (to V_DD1.8 V, NOT V_DDIO)) and a pulldown resistor of the recommended value to set other three possible addresses may be used. See Table 5.

The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when SCL transitions Low while SDA is High. A STOP occurs when SDA transition High while SCL is also HIGH. See Figure 22.

Figure 22. Start and Stop Conditions

To communicate with a remote device, the host controller (master) sends the slave address and listens for a response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is addressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus low. If the address doesn't match a device's slave address, it Not-acknowledges (NACKs) the master by letting SDA be pulled High. ACKs also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs after every data byte is successfully received. When the master is reading data, the master ACKs after every data byte is received to let the slave know it wants to receive another data byte. When the master wants to stop reading, it NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus begins with either a Start condition or a Repeated Start condition. All communication on the bus ends with a Stop condition. A READ is shown in Figure 23 and a WRITE is shown in Figure 24.

If the Serial Bus is not required, the three pins may be left open (NC).

Figure 23. Serial Control Bus — Read

Figure 24. Serial Control Bus — Write

Table 6. Serial Bus Control Registers

ADD (dec)	ADD (hex)	REGISTER NAME	BIT(S)	R/W	DEFAULT (bin)	FUNCTION	DESCRIPTION
0	0	Ser Config 1	7	R/W	0	Reserved	Reserved
			6	R/W	0	MAPSEL	0: LSB on RxIN3 1: MSB on RxIN3
			5	R/W	0	VODSEL	0: Low 1: High
			4	R/W	0	Reserved	Reserved
			3:2	R/W	00	CONFIG	00: Normal Mode, Control Signal Filter DISABLED 01: Normal Mode, Control Signal Filter ENABLED 10: Backwards Compatible (DS90UR124, DS99R124) 11: Backwards Compatible (DS90C124)
			1	R/W	0	SLEEP	Note – not the same function as PowerDown (PDB) 0: normal mode 1: Sleep Mode – Register settings retained.
			0	R/W	0	REG	0: Configurations set from control pins 1: Configuration set from registers (except I2C_ID)
1	1	Device ID	7	R/W	0	REG ID	0: Address from ID[x] Pin 1: Address from Register
			6:0	R/W	1101000	ID[x]	Serial Bus Device ID, Five IDs are: 7b '1101 000 (h'68) 7b '1101 001 (h'69) 7b '1101 010 (h'6A) 7b '1101 011 (h'6B) 7b '1101 110 (h'6E) All other addresses are Reserved.
2	2	De-Emphasis Control	7:5	R/W	000	De-Emph Setting	000: set by external Resistor 001: –1 dB 010: –2 dB 011: –3.3 dB 100: –5 dB 101: –6.7 dB 110: –9 dB 111: –12 dB
			4	R/W	0	De-Emph EN	0: De-Emphasis Enabled 1: De-Emphasis Disabled
			3:0	R/W	000	Reserved	Reserved