SNLS316G September   2009  – December 2015 DS90UR907Q-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings—JEDEC
    3. 6.3  ESD Ratings—IEC and ISO
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  DC Electrical Characteristics
    7. 6.7  Recommended Timing for the Serial Control Bus
    8. 6.8  Switching Characteristics
    9. 6.9  DC and AC Serial Control Bus Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Data Transfer
      2. 7.3.2 Operating Modes And Backward Compatibility - Config[1:0]
      3. 7.3.3 Video Control Signal Filter
      4. 7.3.4 Color Bit Mapping Select
      5. 7.3.5 EMI Reduction Features
        1. 7.3.5.1 Spread Spectrum Compatibility
      6. 7.3.6 Signal Quality Enhancers
        1. 7.3.6.1 VOD Select (VODSEL)
        2. 7.3.6.2 De-Emphasis (De-Emph)
      7. 7.3.7 Power Saving Features
        1. 7.3.7.1 Power-Down Feature (PDB)
        2. 7.3.7.2 Stop Clock Feature
        3. 7.3.7.3 1.8-V or 3.3-V VDDIO Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operating Modes and Backward Compatibility (Config[1:0])
    5. 7.5 Programming
      1. 7.5.1 Optional Serial Bus Control
      2. 7.5.2 Built In Self Test (BIST)
      3. 7.5.3 Optional Serial Bus Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Power-Up Requirements and PDB Pin
      2. 8.1.2 Transmission Media
      3. 8.1.3 Alternate Color / Data Mapping
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PCB Layout and Power System Considerations
      2. 10.1.2 LVDS Interconnect Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • NJK|36
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Power Supply Recommendations

The VDD (VDDn and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower than 1.5 ms, then a capacitor on the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage. When PDB pin is pulled to VDDIO, TI recommends using a 10-kΩ pullup and a >10-μF capacitor to GND to delay the PDB input signal.

All inputs must not be driven until all supply voltages have reached their steady-state value.