SNLS316G September   2009  – December 2015 DS90UR907Q-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings—JEDEC
    3. 6.3  ESD Ratings—IEC and ISO
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  DC Electrical Characteristics
    7. 6.7  Recommended Timing for the Serial Control Bus
    8. 6.8  Switching Characteristics
    9. 6.9  DC and AC Serial Control Bus Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Data Transfer
      2. 7.3.2 Operating Modes And Backward Compatibility - Config[1:0]
      3. 7.3.3 Video Control Signal Filter
      4. 7.3.4 Color Bit Mapping Select
      5. 7.3.5 EMI Reduction Features
        1. 7.3.5.1 Spread Spectrum Compatibility
      6. 7.3.6 Signal Quality Enhancers
        1. 7.3.6.1 VOD Select (VODSEL)
        2. 7.3.6.2 De-Emphasis (De-Emph)
      7. 7.3.7 Power Saving Features
        1. 7.3.7.1 Power-Down Feature (PDB)
        2. 7.3.7.2 Stop Clock Feature
        3. 7.3.7.3 1.8-V or 3.3-V VDDIO Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operating Modes and Backward Compatibility (Config[1:0])
    5. 7.5 Programming
      1. 7.5.1 Optional Serial Bus Control
      2. 7.5.2 Built In Self Test (BIST)
      3. 7.5.3 Optional Serial Bus Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Power-Up Requirements and PDB Pin
      2. 8.1.2 Transmission Media
      3. 8.1.3 Alternate Color / Data Mapping
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PCB Layout and Power System Considerations
      2. 10.1.2 LVDS Interconnect Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • NJK|36
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

NJK Package
36-Pin WQFN
Top View
DS90UR907Q-Q1 30105019.gif

Pin Functions

PIN I/O, TYPE DESCRIPTION
NAME NO.
FPD-LINK INPUT INTERFACE
RxIN[3:0]+ 2, 33, 31, 29 I, LVDS True LVDS Data Input
This pair requires an external 100 Ω termination for standard LVDS levels.
RxIN[3:0]- 1, 34, 32, 30, 28 I, LVDS Inverting LVDS Data Input
This pair requires an external 100 Ω termination for standard LVDS levels.
RxCLKIN+ 35 I, LVDS True LVDS Clock Input
This pair requires an external 100 Ω termination for standard LVDS levels.
RxCLKIN- 34 I, LVDS Inverting LVDS Clock Input
This pair requires an external 100 Ω termination for standard LVDS levels.
CONTROL AND CONFIGURATION
PDB 23 I, LVCMOS
w/ pulldown		 Power-down Mode Input
PDB = 1, Device is enabled (normal operation).
Refer to Power-Up Requirements and PDB Pin in the Applications Information Section.
PDB = 0, Device is powered down
When the Device is in the power-down state, the driver outputs (DOUT+/-) are both logic high, the PLL is shutdown, IDD is minimized. Control Registers are RESET.
VODSEL 20 I, LVCMOS
w/ pulldown		 Differential Driver Output Voltage Select — Pin or Register Control
VODSEL = 1, LVDS VOD is ±450 mV, 900 mVp-p (typical) — Long Cable / De-E Applications
VODSEL = 0, LVDS VOD is ±300 mV, 600 mVp-p (typical)
De-Emph 19 I, Analog
w/ pullup		 De-Emphasis Control — Pin or Register Control
De-Emph = open (float) - disabled
To enable De-emphasis, tie a resistor from this pin to GND or control through register.
See Table 3
MAPSEL 26 I, LVCMOS
w/ pulldown		 FPD-Link Map Select — Pin or Register Control
MAPSEL = 1, MSB on RxIN3+/-. Figure 17
MAPSEL = 0, LSB on RxIN3+/-. Figure 16
CONFIG[1:0] 10, 9 I, LVCMOS
w/ pulldown		 Operating Modes
Determine the device operating mode and interfacing device. Table 1
CONFIG[1:0] = 00: Interfacing to DS90UR906 or DS90UR908, Control Signal Filter DISABLED
CONFIG[1:0] = 01: Interfacing to DS90UR906 or DS90UR908, Control Signal Filter ENABLED
CONFIG [1:0] = 10: Interfacing to DS90UR124, DS99R124
CONFIG [1:0] = 11: Interfacing to DS90C124
ID[x] 4 I, Analog Serial Control Bus Device ID Address Select — Optional
Resistor to Ground and 10-kΩ pullup to 1.8-V rail. See Table 5.
SCL 6 I, LVCMOS Serial Control Bus Clock Input - Optional
SCL requires an external pullup resistor to VDDIO.
SDA 7 I/O, LVCMOS
Open Drain		 Serial Control Bus Data Input / Output - Optional
SDA requires an external pullup resistor VDDIO.
BISTEN 21 I, LVCMOS
w/ pulldown		 BIST Mode — Optional
BISTEN = 1, BIST is enabled
BISTEN = 0, BIST is disabled
RES[7:0] 25, 3, 36, 27, 18, 13, 12, 8 I, LVCMOS
w/ pulldown		 Reserved - tie LOW
FPD-LINK II SERIAL INTERFACE
DOUT+ 16 O, LVDS True Output.
The output must be AC Coupled with a 100 nF capacitor.
DOUT- 15 O, LVDS Inverting Output.
The output must be AC Coupled with a 100 nF capacitor.
POWER AND GROUND
VDDL 5 Power Logic Power, 1.8 V ±5%
VDDP 11 Power PLL Power, 1.8 V ±5%
VDDHS 14 Power TX High Speed Logic Power, 1.8 V ±5%
VDDTX 17 Power Output Driver Power, 1.8 V ±5%
VDDRX 24 Power RX Power, 1.8 V ±5%
VDDIO 22 Power LVCMOS I/O Power and FPD-Link I/O Power 1.8 V ±5% OR 3.3 V ±10%
GND DAP Ground DAP is the large metal contact at the bottom side, located at the center of the WQFN package. Connect to the ground plane (GND) with at least 9 vias.