SNAS425C October   2007  – October 2014 LM98519

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Serial Interface Timing
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Input Clamping and Biasing Circuitry
      2. 7.3.2 Input Connections for 3 Channel Operation
      3. 7.3.3 AFE References
      4. 7.3.4 Offset Control
      5. 7.3.5 Black Level Calibration (Offset)
        1. 7.3.5.1 Manual Offset Adjustment
        2. 7.3.5.2 Automatic Offset Adjustment
        3. 7.3.5.3 Gain Control
        4. 7.3.5.4 White Level Calibration (AGC - Automatic Gain Control)
      6. 7.3.6 Operating Mode Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 AFEPHASEn Details for SHP/SHD Input Mode
      2. 7.4.2 AFEPHASEn Details for SAMPLE and HOLD Input Mode
      3. 7.4.3 AFEPHASEn: 6 Channel and 3 Channel Modes
      4. 7.4.4 LM98519 AFEPHASE Synchronization
      5. 7.4.5 Sampling Timing Diagrams
    5. 7.5 Programming
      1. 7.5.1  Using Black Pixel Average
      2. 7.5.2  Sample Timing Control
      3. 7.5.3  Timing Monitor Outputs
      4. 7.5.4  Output Data Test Pattern Generation
      5. 7.5.5  Fixed Pattern
      6. 7.5.6  Horizontal Gradation
      7. 7.5.7  Vertical Gradation
      8. 7.5.8  Lattice Pattern
      9. 7.5.9  Serial Interface
      10. 7.5.10 Serial Write
      11. 7.5.11 Serial Read
    6. 7.6 Register Maps
      1. 7.6.1 Configuration Registers
      2. 7.6.2 Configuration Register Details
  8. 8 Application and Implementation
    1. 8.1 Design Requirements
    2. 8.2 Detailed Design Procedure
  9. 9 Power Supply Recommendations
    1. 9.1 Over Voltage Protection on OS Inputs
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Design Requirements

See Figure 36 for an example circuit and the required minimum circuitry around the LM98519.

All power supply voltages should be provided from clean linear regulator outputs, NOT switching power supplies.

8.2 Detailed Design Procedure

  1. 3.3-V Power for Analog, Digital, and Outputs (VDDA, VDDD, and VDDO) supplies. It is recommended to use a common LDO regulator for al 3.3 V supplies, using EMI filter devices and dedicated coupling to isolate any noise between buses.
  2. Input Timing Signals (Ground referenced logic signal with: 2.0 V < VHigh < 3.3 V)
    1. MCLK: Continuous clock signal at pixel rate or ADC rate of LM98519
    2. CLPIN: Once per scan line signal used to control input clamp for DC restoration of AC coupled CCD input signals
    3. BLKCLP: Once per scan line signal used to indicate beginning of black pixels for Black (Offset) Level Calibration
    4. AGC_ONB – Input signal used to initiate start of White (Gain) Calibration
    5. SHP/SAMPLE: Once per pixel signal used to control pixel sample timing
    6. SHD/HOLD: Once per pixel signal used to control pixel sample timing
  3. CCD signals at OS Inputs – These are connected to the outputs from the CCD sensor emitter follower buffer circuits. The signals are AC coupled to the AFE inputs using 0.1 uF capacitors.
  4. Serial control interface from data processing module to LM98519 (Ground referenced logic signal with: 2.0 V < Vhigh < 3.3 V):
    1. SENB – Serial enable to LM98519
    2. SCLK – Serial clock input to LM98519
    3. SDI – Data input to LM98519
    4. SDO – Data output from LM98519
  5. Serialized data lines connected to FPGA or chip on data processing module
  6. Adjust and reconfigure the configuration register settings as needed