SNLS568D March   2017  – May 2020 LMH1228

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Block Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Recommended SMBus Interface Timing Specifications
    7. 6.7 Serial Parallel Interface (SPI) Timing Specifications
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 4-Level Input Pins and Thresholds
      2. 7.3.2 OUT0_SEL and SDI_OUT2_SEL Control
      3. 7.3.3 Input Signal Detect
      4. 7.3.4 Continuous Time Linear Equalizer (CTLE)
      5. 7.3.5 Clock and Data (CDR) Recovery
      6. 7.3.6 Internal Eye Opening Monitor (EOM)
      7. 7.3.7 Output Function Control
      8. 7.3.8 Output Driver Control
        1. 7.3.8.1 Line-Side Output Cable Driver (SDI_OUT1+, SDI_OUT2+)
          1. 7.3.8.1.1 Output Amplitude (VOD)
          2. 7.3.8.1.2 Output Pre-Emphasis
          3. 7.3.8.1.3 Output Slew Rate
          4. 7.3.8.1.4 Output Polarity Inversion
        2. 7.3.8.2 Host-Side 100-Ω Output Driver (OUT0±)
      9. 7.3.9 Status Indicators and Interrupts
        1. 7.3.9.1 LOCK_N (Lock Indicator)
        2. 7.3.9.2 SD_N (Signal Detect)
        3. 7.3.9.3 INT_N (Interrupt)
    4. 7.4 Device Functional Modes
      1. 7.4.1 System Management Bus (SMBus) Mode
        1. 7.4.1.1 SMBus Read and Write Transaction
          1. 7.4.1.1.1 SMBus Write Operation Format
          2. 7.4.1.1.2 SMBus Read Operation Format
      2. 7.4.2 Serial Peripheral Interface (SPI) Mode
        1. 7.4.2.1 SPI Read and Write Transactions
        2. 7.4.2.2 SPI Write Transaction Format
        3. 7.4.2.3 SPI Read Transaction Format
        4. 7.4.2.4 SPI Daisy Chain
    5. 7.5 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 SMPTE Requirements and Specifications
      2. 8.1.2 Low-Power Optimization
      3. 8.1.3 Optimized Loop Bandwidth Settings for Arria 10 FPGA Applications
    2. 8.2 Typical Applications
      1. 8.2.1 Dual Cable Driver
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Distribution Amplifier
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Stack-Up and Ground References
      2. 10.1.2 High-Speed PCB Trace Routing and Coupling
        1. 10.1.2.1 SDI_OUT1± and SDI_OUT2±:
        2. 10.1.2.2 IN0± and OUT0±:
      3. 10.1.3 Anti-Pads
      4. 10.1.4 BNC Connector Layout and Routing
      5. 10.1.5 Power Supply and Ground Connections
      6. 10.1.6 Footprint Recommendations
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Export Control Notice
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information
      2. 12.1.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

RTV Package
32-Pin WQFN
Top View
LMH1228 pin_out_diagram_snls575.gif

Pin Functions

PIN I/O(1) DESCRIPTION
NAME NO.
HIGH-SPEED DIFFERENTIAL I/OS
SDI_OUT1+ 1 I/O, Analog Single-ended complementary outputs with on-chip 75-Ω termination at SDI_OUT1+ and SDI_OUT1–. SDI_OUT1± include integrated return loss networks designed to meet the SMPTE output return loss requirements. Connect SDI_OUT1+ to a BNC through a 4.7-µF, AC-coupling capacitor. SDI_OUT1– should be similarly AC-coupled and terminated with an external 4.7-µF capacitor and 75-Ω resistor to GND.
SDI_OUT1– 2 I/O, Analog
SDI_OUT2+ 8 O, Analog Single-ended complementary outputs with on-chip 75-Ω termination at SDI_OUT2+ and SDI_OUT2–. SDI_OUT2± include integrated return loss networks designed to meet the SMPTE output return loss requirements. SDI_OUT2± is used as a second cable driver. Connect SDI_OUT2+ to a BNC through a 4.7-µF, AC-coupling capacitor. SDI_OUT2– should be similarly AC-coupled and terminated with an external 4.7-µF capacitor and 75-Ω resistor to GND.
SDI_OUT2– 7 O, Analog
IN0+ 19 I, Analog Differential inputs from host video processor. On-chip 100-Ω differential termination. Requires external 4.7-µF, AC-coupling capacitors for SMPTE applications.
IN0– 18 I, Analog
OUT0+ 23 O, Analog Differential outputs to host video processor. On-chip 100-Ω differential termination. Requires external 4.7-µF, AC-coupling capacitors for SMPTE applications.
OUT0– 22 O, Analog
CONTROL PINS
OUT0_SEL 4 I, LVCMOS OUT0_SEL enables the use of the 100-Ω host-side output driver at OUT0±.
See Table 2 for details.
OUT0_SEL is internally pulled high by default (OUT0 disabled).
HOST_EQ0 9 I, 4-LEVEL HOST_EQ0 selects the equalizer setting for IN0±.
See Table 4 for details.
MODE_SEL 12 I, 4-LEVEL MODE_SEL enables the SPI or SMBus serial control interface.
See Table 9 for details.
SDI_OUT2_SEL 14 I, LVCMOS SDI_OUT2_SEL enables the use of the 75-Ω output driver at SDI_OUT2±.
See Table 2 for details.
SDI_OUT2_SEL is internally pulled high by default (SDI_OUT2 disabled).
OUT_CTRL 17 I, 4-LEVEL OUT_CTRL selects the signal being routed to the output. It is used to enable or bypass the reclocker.
See Table 6 for details.
SDI_VOD 24 I, 4-LEVEL SDI_VOD selects one of four output amplitudes for the cable drivers at SDI_OUT1± and SDI_OUT2±.
See Table 7 for details.
LOCK_N 27 O, LVCMOS,
OD		 LOCK_N is the reclocker lock indicator. LOCK_N is pulled low when the reclocker has acquired lock condition. LOCK_N is a 3.3-V tolerant, open-drain output. It requires an external resistor to a logic supply.
LOCK_N can be reconfigured to indicate Signal Detector (SD_N) or Interrupt (INT_N) through register programming. See Status Indicators and Interrupts.
ENABLE 32 I, LVCMOS A logic-high at ENABLE enables normal operation for the LMH1228. A logic-low at ENABLE places the LMH1228 in Power-Down Mode.
ENABLE is internally pulled high by default.
SPI SERIAL CONTROL INTERFACE, MODE_SEL = F (FLOAT)
SS_N 11 I, LVCMOS SS_N is the Slave Select. When SS_N is at logic Low, it enables SPI access to the LMH1228 slave device.
SS_N is a 2.5-V LVCMOS input and is internally pulled high by default.
MOSI 13 I, LVCMOS MOSI is the SPI serial control data input to the LMH1228 slave device when the SPI bus is enabled. MOSI is a 2.5-V LVCMOS input.
An external pullup resistor is recommended.
MISO 28 O, LVCMOS MISO is the SPI serial control data output from the LMH1228 slave device.
MISO is a 2.5-V LVCMOS output.
SCK 29 I, LVCMOS SCK is the SPI serial input clock to the LMH1228 slave device when the SPI interface is enabled. SCK is a 2.5-V LVCMOS input.
An external pullup resistor is recommended.
SMBUS SERIAL CONTROL INTERFACE, MODE_SEL = L (1 KΩ TO VSS)
ADDR0 11 Strap, 4-LEVEL ADDR[1:0] are 4-level straps, read into the device at power up. They are used to select one of the 16 supported SMBus addresses when SMBus is enabled. See Table 10 for details.
SDA 13 I/O, LVCMOS,
OD		 SDA is the SMBus bidirectional data line to or from the LMH1228 slave device when SMBus is enabled. SDA is an open-drain I/O and requires an external pullup resistor to the SMBus termination voltage. SDA is 3.3-V tolerant.
ADDR1 28 Strap, 4-LEVEL ADDR[1:0] are 4-level straps, read into the device at power up. They are used to select one of the 16 supported SMBus addresses when SMBus is enabled. See Table 10 for details.
SCL 29 I/O, LVCMOS,
OD		 SCL is the SMBus input clock to the LMH1228 slave device when SMBus is enabled. It is driven by a LVCMOS open-drain driver from the SMBus master. SCL requires an external pullup resistor to the SMBus termination voltage. SCL is 3.3-V tolerant.
RESERVED
RSV1
RSV2
RSV3
RSV4
RSV5 		10
15
16
25
26 		— Reserved pins. Do not connect.
RSV6 5 I, LVCMOS Reserved pin. This input must be tied high with 1-kΩ resistor to VIN. Alternatively, this pin setting can be overridden by register control. Refer to the LMH1228 and LMH1208 Programming Guide (SNAU206) for more details.
POWER
VSS 3, 6, 20 I, Ground Ground reference.
VDD_CDR 21 I, Power VDD_CDR powers the reclocker circuitry. It is connected to the same 2.5-V ± 5% supply as VIN.
VIN 30 I, Power VIN is connected to an external 2.5-V ± 5% power supply.
VDD_LDO 31 O, Power VDD_LDO is the output of the internal 1.8-V LDO regulator. VDD_LDO output requires an external 1-µF and 0.1-µF bypass capacitor to VSS. The internal LDO is designed to power internal circuitry only.
EP — I, Ground EP is the exposed pad at the bottom of the RTV package. The exposed pad should be connected to the VSS plane through a 3 × 3 via array.
(1) I = Input, O = Output, I/O = Input or Output, OD = Open Drain, LVCMOS = 2-State Logic, 4-LEVEL = 4-State Logic