SNAS739D June 2018 – May 2020 LMX2615-SP
PRODUCTION DATA.
The state machine clock is a divided down version of the OSCin signal that is used internally in the device. This divide value 1, 2, 4, 8, or 16 and is determined by CAL_CLK_DIV programming word (described in the programming section). This state machine clock impacts various features like the VCO calibration and ramping. The state machine clock is calculated as fsmclk = fOSC / 2CAL_CLK_DIV.