SNVS174I February   2003  – February 2015 LP3852 , LP3855

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematics
  5. 5 Revision History
  6. 6 Voltage Options
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
      1. 9.3.1 SENSE Pin
      2. 9.3.2 SHUTDOWN (SD) Operation
      3. 9.3.3 Dropout Voltage
      4. 9.3.4 Reverse Current Path
      5. 9.3.5 Short-Circuit Protection
      6. 9.3.6 ERROR Flag Operation
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operation with VOUT(TARGET) + 0.1 V ≤ VIN ≤ 7 V
      2. 9.4.2 Operation With SD Pin Control
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 External Capacitors
          1. 10.2.2.1.1 Input Capacitor
          2. 10.2.2.1.2 Output Capacitor
        2. 10.2.2.2 Operation with Ceramic Output Capacitors
        3. 10.2.2.3 Selecting A Capacitor
        4. 10.2.2.4 Capacitor Characteristics
          1. 10.2.2.4.1 Ceramic
          2. 10.2.2.4.2 Tantalum
          3. 10.2.2.4.3 Aluminum
        5. 10.2.2.5 Turnon Characteristics For Output Voltages Programmed to 2 V or Below
        6. 10.2.2.6 Output Noise
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 RFI and/or EMI Susceptibility
    4. 12.4 Power Dissipation/Heatsinking
      1. 12.4.1 Heatsinking TO-220 Package
      2. 12.4.2 Heatsinking TO-263 Package
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Detailed Description

9.1 Overview

The LP3852 and LP3855 series of fast ultra-low dropout linear regulators operate from a 2.5-V to 7-V input supply. A wide range of preset output voltage options are available. These ultra-low dropout linear regulators respond very quickly to step changes in load, which makes them suitable for low voltage microprocessor applications. The LP3852 and LP3855 are developed on a CMOS process which allows low quiescent current operation independent of output load current. This CMOS process also allows the LP3852 and LP3855 to operate under extremely low dropout conditions.

9.2 Functional Block Diagrams

LP3852 LP3855 20031003.pngFigure 14. LP3852 Block Diagram
LP3852 LP3855 20031029.pngFigure 15. LP3855 Block Diagram

9.3 Feature Description

9.3.1 SENSE Pin

In applications where the regulator output is not very close to the load, LP3855 can provide better remote load regulation using the SENSE pin. Figure 16 depicts the advantage of the SENSE option. The LP3852 regulates the voltage at the OUT pin. Hence, the voltage at the remote load will be the regulator output voltage minus the drop across the trace resistance. For example, in the case of a 3.3-V output, if the trace resistance is 100 mΩ, the voltage at the remote load will be 3.15 V with 1.5 A of load current, ILOAD. The LP3855 regulates the voltage at the SENSE pin. Connecting the SENSE pin to the remote load will provide regulation at the remote load, as shown in Figure 16. If the SENSE pin is not required, the SENSE pin must be connected to the OUT pin.

LP3852 LP3855 20031008.pngFigure 16. Improving Remote Load Regulation Using LP3855

9.3.2 SHUTDOWN (SD) Operation

A CMOS Logic low level signal at the SD pin will turn off the regulator. SD must be actively terminated through a 10-kΩ pullup resistor for a proper operation. If this pin is driven from a source that actively pulls high and low (such as a CMOS rail-to-rail comparator), the pullup resistor is not required. This pin must be tied to VIN if not used.

The SD pin threshold has no voltage hysteresis. If the SD pin is actively driven, the voltage transition must rise and fall cleanly and promptly.

9.3.3 Dropout Voltage

The dropout voltage of a regulator is defined as the minimum input-to-output differential required to stay within 2% of the nominal output voltage. For CMOS LDOs, the dropout voltage is the product of the load current and the Rds(on) of the internal MOSFET.

9.3.4 Reverse Current Path

The internal MOSFET in LP3852 and LP3855 has an inherent parasitic diode. During normal operation, the input voltage is higher than the output voltage and the parasitic diode is reverse biased. However, if the output is pulled above the input in an application, then current flows from the output to the input as the parasitic diode gets forward biased. The output can be pulled above the input as long as the current in the parasitic diode is limited to 200-mA continuous and 1-A peak.

9.3.5 Short-Circuit Protection

The LP3852 and LP3855 are short-circuit protected and in the event of a peak overcurrent condition, the short-circuit control loop will rapidly drive the output PMOS pass element off. Once the power pass element shuts down, the control loop will rapidly cycle the output on and off until the average power dissipation causes the thermal shutdown circuit to respond to servo the on/off cycling to a lower frequency. Please refer to for power dissipation calculations.

9.3.6 ERROR Flag Operation

The LP3852 and LP3855 produce a logic low signal at the ERROR pin when the output drops out of regulation due to low input voltage, current limiting, or thermal limiting. This flag has a built in hysteresis. The timing diagram in Figure 17 shows the relationship between the ERROR flag and the output voltage. In this example, the input voltage is changed to demonstrate the functionality of the ERROR Flag.

The internal ERROR comparator has an open drain output stage; thus, the ERROR pin should be pulled high through a pullup resistor. Although the ERROR flag pin can sink current of 1 mA, this current is energy drain from the input supply. Hence, the value of the pullup resistor should be in the range of 10 kΩ to 1 MΩ. The ERROR pin must be connected to ground if this function is not used. It should also be noted that when the shutdown pin is pulled low, the ERROR pin is forced to be invalid for reasons of saving power in shutdown mode.

LP3852 LP3855 20031007.pngFigure 17. ERROR Operation

9.4 Device Functional Modes

9.4.1 Operation with VOUT(TARGET) + 0.1 V ≤ VIN ≤ 7 V

The device operate if the input voltage is equal to, or exceeds VOUT(TARGET) + 0.1 V. At input voltages below the minimum VIN requirement, the devices do not operate correctly and output voltage may not reach target value.

9.4.2 Operation With SD Pin Control

A CMOS Logic low level signal at the SD pin will turn off the regulator. The SD pin must be actively terminated through a 10-kΩ pullup resistor for a proper operation.