7.3.1 Equalizer

The data signal is applied to an input equalizer by means of the input signal pins DIN+ / DIN–, which provide on-chip differential 100-Ω line termination. The equalizer is enabled by default and can be disabled by setting the transmitter equalizer disable bit TXEQ_DIS = 1 (bit 1 of register 10). Equalization of up to 300 mm (12 inches) of microstrip or stripline transmission line on FR4 printed circuit boards can be achieved. The amount of equalization is set through register settings TXCTLE [0..3] (register 11). The device can accept input amplitude levels from 100 mVpp up to 1000 mVpp.

7.3.2 CDR

The clock and data recovery function consists of a Phase-Locked Loop (PLL) and retimer. The CDR can be operated without a reference clock and the Voltage Controlled Oscillator (VCO) can cover 9.8 Gbps to 11.7 Gbps data rates. The PLL is phase locked to the incoming data stream and attenuates the high frequency jitter on the data, producing a recovered clean clock with substantially reduced jitter. An external capacitor for the PLL loop filter is connected to the LF pin. A value of 2.2 nF is recommended. The clean clock is used to retime the incoming data, producing an output signal with reduced jitter, and in effect, resetting the jitter budget for the transmitter.

The CDR is enabled by default. The CDR can be disabled and bypassed by setting the transmitter CDR disable bit TXCDR_DIS = 1 (bit 4 of register 10). Alternatively, the CDR can be left powered on but bypassed by setting the transmitter CDR bypass bit TX_CDRBP = 1 (bit 3 of register 10).

The CDR is designed to meet the XFP Datacom requirements and Telecom requirements for a maximum of 1-dB jitter peaking at a frequency greater than 120 kHz. The CDR is not designed to meet the Telecom regenerator requirements of jitter peaking less than 0.03 dB at a frequency less than 120 kHz. The default CDR bandwidth is typically 4.5 MHz and can be adjusted using the SEL_RES[0..2] bits (bits 5 to 7 of register 51). Adjusting these bits changes the bandwidth of both the transmitter and receiver CDRs.

For the majority of applications, the default settings in register 19 for the transmitter CDR can be used. However, for some applications or for test purposes, some modes of operation may be useful. The frequency detector for the PLL is set to an automatic mode of operation by default. When a signal is applied to the transmitter input the frequency detector search algorithm will be initiated to determine the frequency of the data. The default algorithm ensures a fast CDR lock time of less than 2 ms. The fast lock can be disabled by setting the transmitter CDR fast lock disable bit TXFL_DIS = 1 (bit 3 of register 19). Once the frequency has been detected then the frequency detector will be disabled and the supply current will decrease by approximately 10mA. In some applications, such as when there are long periods of idle data, it may be advantageous to keep the frequency detector permanently enabled by setting the transmitter frequency detector enable bit TXFD_EN = 1 (bit 5 of register 19). For test purposes, the frequency detector can be permanently disabled by setting the transmitter frequency detector disable bit TXFD_DIS = 1 (bit 4 of register 19). For fast lock times the frequency detector can be set to one of two preselected data rates using the transmitter frequency detection mode selection bits TXFD_MOD[0..1] (bits 6 and 7 of register 19). If it is desired to use the retimer at lower data rates than the standard 9.8 to 11.7Gbps then the transmitter divider ratio should be adjusted accordingly through TXDIV[0..2] (bits 0 to 2 of register 19). For example, for re-timed operation at 2.5 Gbps the divider should be set to divide by 4.

7.3.3 Modulator Driver

The modulation current is sunk from the common emitter node of the limiting output driver differential pair by means of a modulation current generator, which is digitally controlled by the 2-wire serial interface.

The collector nodes of the output stages are connected to the transmitter output pins TXOUT+ and TXOUT–. The collectors have internal 50Ω back termination resistors to VCC_TX. The outputs are optimized to drive a 50 Ω single-ended load and to obtain the maximum single-ended output voltage of 2.0Vpp, AC coupling and inductive pull-ups to VCC are required. For reduced power consumption the DC resistance of the inductive pull-ups should be minimized to provide sufficient headroom on the TXOUT+ and TXOUT– pins.

The polarity of the output pins can be inverted by setting the transmitter output polarity switch bit, TXOUTPOL (bit 5 of register 10) to 1. In addition, the output driver can be disabled by setting the transmitter output driver disable bit TXOUT_DIS = 1 (bit 6 of register 10).

The output driver is set to differential output by default. In order to reduce the power consumption for single-ended applications driving an electroabsorptive modulated laser (EML) the output drive register 13 should be set to single-ended mode. The single-ended output signal is enabled by setting the transmitter mode select bit TXMODE = 1 (bit 6 of register 13). The positive output is active by default. To enable the negative output and disable the positive output set TXOUTSEL = 1 (bit 7 of register 13).

Output de-emphasis can be applied to the signal by adjusting the transmitter de-emphasis bits TXDEADJ[0..3] (bits 0 to 3 of register 13). In addition, the width of the applied de-emphasis can be increased by setting the transmitter output peaking width TXPKSEL = 1 (bit 6 of register 11). The wide peaking width would typically be useful for a more capacitive transmitter load. How de-emphasis is applied is controlled through the TXSTEP bit (bit 5 of register 13). Setting TXSTEP = 1 delays the time of the applied de-emphasis and has more of an impact on the falling edge. A graphical representation of the two de-emphasis modes is shown in Figure 23. Using de-emphasis can help to optimize the transmitted output signal; however, it will add to the power consumption.

The output edge speed can be set to slow mode of operation through the TXSLOW bit (bit 4 of register 13). For transmitter modulation output settings (TXMOD - register 12) below 0xC0 it is recommended to set TXSLOW = 1 to reduce the output jitter.

Figure 23. Transmitter De-Emphasis Modes

7.3.4 Modulation Current Generator

The modulation current generator provides the current for the high speed output driver described above. The circuit can be digitally controlled through the 2-wire interface block or controlled by applying an analog voltage in the range of 0 to 2 V to the AMP pin. The default method of control is through the 2-wire interface. To use the AMP pin set the transmitter amplitude control bit TXAMPCTRL = 1 (bit 0 of register 10).

An 8-bit wide control bus, TXMOD[0..7] (register 12), is used to set the desired modulation current and the output voltage.

The entire transmitter signal path, including CDR, can be disabled and powered down by setting TX_DIS = 1 (bit 7 of register 10).

7.3.5 DC Offset Cancellation and Cross Point Control

The ONET1131EC transmitter has DC offset cancellation to compensate for internal offset voltages. The offset cancellation can be disabled by setting TXOC_DIS = 1 (bit 2 of register 10).

The crossing point can be moved toward the one level by setting TXCPSGN = 1 (bit 7 of register 14) and it can be moved toward the zero level by setting TXCPSGN = 0. The percentage of shift depends upon the register settings of the transmitter cross-point adjustment bits TXCPADJ[0..6] (register 14).

7.3.6 Bias Current Generation and APC Loop

The bias current for the laser is turned off by default and has to be enabled by setting the laser bias current enable bit TXBIASEN = 1 (bit 2 of register 1). In open loop operation, selected by setting TXOLENA = 1 (bit 4 of register 1), the bias current is set directly by the 10-bit wide control word TXBIAS[0..9] (register 15 and register 16). In Automatic Power Control (APC) mode, selected by setting TXOLENA = 0, the bias current depends on the register settings TXBIAS[0..9] and the coupling ratio (CR) between the laser bias current and the photodiode current. CR = I_BIAS/I_PD. If the photodiode cathode is connected to VCC and the anode is connected to the PD pin (PD pin is sinking current) set TXPDPOL = 1 (bit 0 of register 1). If the photodiode anode is connected to ground and the cathode is connected to the PD pin (PD pin is sourcing current), set TXPDPOL = 0.

Three photodiode current ranges can be selected by means of the photodiode current range bits TXPDRNG[0..1] (bits 5 and 6 of register 1). The photodiode range should be chosen to keep the laser bias control DAC, TXBIAS[0..9], close to the center of its range. This keeps the laser bias current set point resolution high. For details regarding the bias current setting in open-loop mode as well as in closed-loop mode, see the Register Mapping table.

The ONET1131EC has the ability to source or sink the bias current. The default condition is for the BIAS pin to source the current (TXBIASPOL = 0). To act as a sink, set TXBIASPOL = 1 (bit 1 of register 1).

The bias current is monitored using a current mirror with a gain equal to 1/100. By connecting a resistor between MONB and GND, the bias current can be monitored as a voltage across the resistor. A low temperature coefficient precision resistor should be used. The bias current can also be monitored as a 10 bit unsigned digital word by setting the transmitter bias current digital monitor selection bit TXDMONB = 1 (bit 5 of register 16) and removing the resistor from MONB to ground.

The photodiode current is monitored using a current mirror with various gains that are dependent upon the photodiode current range being used. By connecting a resistor between MONP and GND, the photodiode current can be monitored as a voltage across the resistor. A low temperature coefficient precision resistor should be used. The photodiode current can also be monitored as a 10 bit unsigned digital word by setting the transmitter photodiode current digital monitor selection bit TXDMONP = 1 (bit 6 of register 16) and removing the resistor from MONP to ground.

7.3.7 Laser Safety Features and Fault Recovery Procedure

The ONET1131EC provides built in laser safety features. The following fault conditions are detected if the transmitter fault detection enable bit TXFLTEN = 1 (bit 3 of register 1):

1. Voltage at MONB exceeds the bandgap voltage (1.2 V) or, alternately, if TXDMONB = 1 and the bias current exceeds the bias current monitor fault threshold set by TXBMF[0..7] (register 17). When using the digital monitor, the resistor from the MONB pin to ground must be removed.
2. Voltage at MONP exceeds the bandgap voltage (1.2 V) and the analog photodiode current monitor fault trigger bit, TXMONPFLT (bit 7 of register 1), is set to 1. Alternately, a fault can be triggered if TXDMONP = 1 and the photodiode current exceeds the photodiode current monitor fault threshold set by TXPMF[0..7] (register 18). When using the digital monitor, the resistor from the MONP pin to ground must be removed.
3. Photodiode current exceeds 150% of its set value,
4. Bias control DAC drops in value by more than 50% in one step.

If the fault detection is being used then to avoid a fault from occurring at start-up it is recommended to set up the required bias current and APC loop conditions first and enable the laser bias current (TXBIASEN = 1) as the last step in the sequence of commands.

If one or more fault conditions occur and the transmitter fault enable bit TXFLTEN is set to 1, the ONET1131EC responds by:

1. Setting the bias current to zero.
2. Asserting and latching the TX_FLT pin.
3. Setting the TX_FLT bit (bit 5 of register 43) to 1.

Fault recovery is performed by the following procedure:

1. The transmitter disable pin TX_DIS and/or the transmitter bias current enable bit TXBIASEN are toggled for at least the fault latch reset time.
2. The TX_FLT pin de-asserts while the transmitter disable pin TX_DIS is asserted or the transmitter bias current enable bit TXBIASEN is de-asserted.
3. If the fault condition is no longer present, the part returns to normal operation with its prior output settings after the disable negate time.
4. If the fault condition is still present, TX_FLT re-asserts once TX_DIS is set to a low level and/or TXBIASEN is set to 0 and the part will not return to normal operation.

7.3.8 Analog Block

7.3.9 Acknowledge

Each receiving device, when addressed, is obliged to generate an acknowledge bit. The transmitter releases the SDA line and a device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge clock pulse. Setup and hold times must be taken into account. When a slave-receiver doesn’t acknowledge the slave address, the data line must be left HIGH by the slave. The master can then generate a STOP condition to abort the transfer. If the slave-receiver does acknowledge the slave address but some time later in the transfer cannot receive any more data bytes, the master must abort the transfer. This is indicated by the slave generating the not acknowledge on the first byte to follow. The slave leaves the data line HIGH and the master generates the STOP condition, see Figure 2.

7.4.1 Differential Transmitter Output

Operation with differential output is the default mode of operation. This mode is intended for externally modulated lasers requiring differential drive such as Mach Zehnder modulators.

7.4.2 Single-Ended Transmitter Output

In order to reduce the power consumption for single-ended EML applications the output driver should be set to single-ended mode. The single-ended output signal can be enabled by setting the transmitter mode select bit TXMODE = 1 (bit 6 of register 13). The positive output is active by default. To enable the negative output and disable the positive output set TXOUTSEL = 1 (bit 7 of register 13).

7.6.1 R/W Control Registers

7.6.2 TX Registers

7.6.3 Reserved Registers

7.6.4 Read Only Registers

7.6.5 Adjustment Registers