SBOS206F January   2001  – October 2023 OPA561

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Feature Description
      1. 6.2.1 Adjustable Current Limit
        1. 6.2.1.1 Current Limit Accuracy
        2. 6.2.1.2 Setting the Current Limit
      2. 6.2.2 Enable-Status (E/S) Pin
        1. 6.2.2.1 Output Disable
        2. 6.2.2.2 Maintaining Microcontroller Compatibility
      3. 6.2.3 Overcurrent Flag
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Output Stage Compensation
      2. 7.1.2 Output Protection
      3. 7.1.3 Thermal Protection
      4. 7.1.4 Power Dissipation
      5. 7.1.5 Heat-Sink Area
      6. 7.1.6 Amplifier Mounting
        1. 7.1.6.1 What is the PowerPAD™ Integrated Circuit Package?
        2. 7.1.6.2 PowerPAD™ Integrated Circuit Package Assembly Process
    2. 7.2 Typical Application
      1. 7.2.1 Laser Diode Driver
      2. 7.2.2 Programmable Power Supply
      3. 7.2.3 Power-Line Communication Modem
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PWP|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.1 Layout Guidelines

The OPA561 is a high-speed power amplifier that requires proper layout for best performance. Figure 7-9 shows an example of proper layout.

Keep power-supply leads as short as possible, which keeps inductance low and resistive losses at a minimum. A minimum 18-gauge wire thickness is recommended for power-supply leads. Use a wire length < 8 inches.

Proper power-supply bypassing with low-ESR capacitors is essential to achieve good performance. A parallel combination of small ceramic (around 100 nF) and larger (47 μF) nonceramic bypass capacitors provide low impedance over a wide frequency range. Place bypass capacitors as close as practical to the power-supply pins of the OPA561.

Keep PCB traces conducting high currents, such as from output to load or from the power-supply connector to the power-supply pins of the OPA561, as wide and as short as possible. This guideline helps keep inductance low and resistive losses to a minimum.

The holes in the landing pattern for the OPA561 are for the thermal vias that connect the thermal pad of the OPA561 to the heat sink area on the printed circuit board (see attached Land Pattern mechanical drawing). The additional larger vias further enhance the heat conduction into the heat-sink area. All traces conducting high currents are very wide for lowest inductance and minimal resistive losses. The negative supply (V−) pin on the OPA561 is connected through the thermal pad. This connection allows for maximum trace width for VOUT and the positive power supply (V+).