SLLS736B July   2006  – March 2024 SN65MLVD047A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Package Dissipation Ratings
    5. 5.5 Thermal Information
    6. 5.6 Device Electrical Characteristics
    7. 5.7 Device Electrical Characteristics
    8. 5.8 Switching Characteristics
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Synchroization Clock in AdvancedTCA
      2. 8.1.2 Multipoint Configuration
      3. 8.1.3 Multidrop Configuration
      4. 8.1.4 Unused Channel
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.4 Package Dissipation Ratings

PACKAGEPCB JEDEC
STANDARD		TA ≤ 25°C
POWER RATING		DERATING FACTOR
ABOVE TA = 25°C(1)		TA = 85°C
POWER RATING
D(16)Low-K(2)898mW7.81mW/°C429mW
PW(16)Low-K(2)592mW5.15mW/°C283mw
High-K(3)945mW8.22mW/°C452mw
(1) This is the inverse of the junction-to-ambient thermal resistance when board mounted and with no air flow.
(2) In accordance with the Low-K thermal metric definitions of EIA/JESD51-3.
(3) In accordance with the High-K thermal metric definitions of EIA/JESD51-7.