SCES681E January   2008  – April 2024 SN74AUP2G08

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Resistance Characteristics
    5. 5.5  Electrical Characteristics
    6. 5.6  Switching Characteristics - CL = 5 pF
    7. 5.7  Switching Characteristics - CL = 10 pF
    8. 5.8  Switching Characteristics - CL = 15 pF
    9. 5.9  Switching Characteristics - CL = 30 pF
    10. 5.10 Operating Characteristics
    11. 5.11 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 19
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS Push-Pull Outputs
      2. 7.3.2 CMOS Schmitt-Trigger Inputs
      3. 7.3.3 Partial Power Down (Ioff)
      4. 7.3.4 Standard CMOS Inputs
      5. 7.3.5 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Wide operating VCC range of 0.8V to 3.6V
  • Low static-power consumption
    (ICC = 0.9μA max)
  • Low dynamic-power consumption
    (Cpd = 4.3pF typ at 3.3V)
  • Low noise – overshoot and undershoot
    <10% of VCC
  • Ioff supports partial-power-down mode operation
  • Schmitt-trigger action allows slow input transition and better switching noise immunity at the input
    (Vhys = 250mV Typ at 3.3V)
  • 3.6V I/O tolerant to support mixed-mode signal operation
  • tpd = 5.9ns max at 3.3V
  • Latch-up performance exceeds 100mA per JESD 78, Class II