SLASF30 January   2022 TAA5212

ADVANCE INFORMATION  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: I2C Interface
    7. 6.7  Switching Characteristics: I2C Interface
    8. 6.8  Timing Requirements: SPI Interface
    9. 6.9  Switching Characteristics: SPI Interface
    10. 6.10 Timing Requirements: TDM, I2S or LJ Interface
    11. 6.11 Switching Characteristics: TDM, I2S or LJ Interface
    12. 6.12 Timing Requirements: PDM Digital Microphone Interface
    13. 6.13 Switching Characteristics: PDM Digial Microphone Interface
  8. Parameter Measurement Information
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Hardware Control
      2. 8.3.2 Serial Interfaces
        1. 8.3.2.1 Control Serial Interfaces
        2. 8.3.2.2 Audio Serial Interfaces
          1. 8.3.2.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 8.3.2.2.2 Inter IC Sound (I2S) Interface
          3. 8.3.2.2.3 Left-Justified (LJ) Interface
        3. 8.3.2.3 Using Multiple Devices With Shared Buses
      3. 8.3.3 Phase-Locked Loop (PLL) and Clock Generation
      4. 8.3.4 Input Channel Configurations
      5. 8.3.5 Reference Voltage
      6. 8.3.6 Programmable Microphone Bias
      7. 8.3.7 Signal-Chain Processing
        1. 8.3.7.1 ADC Signal-Chain
          1. 8.3.7.1.1 Programmable Channel Gain and Digital Volume Control
          2. 8.3.7.1.2 Programmable Channel Gain Calibration
          3. 8.3.7.1.3 Programmable Channel Phase Calibration
          4. 8.3.7.1.4 Programmable Digital High-Pass Filter
          5. 8.3.7.1.5 Programmable Digital Biquad Filters
          6. 8.3.7.1.6 Programmable Channel Summer and Digital Mixer
          7. 8.3.7.1.7 Configurable Digital Decimation Filters
            1. 8.3.7.1.7.1 Linear Phase Filters
              1. 8.3.7.1.7.1.1 Sampling Rate: 16 kHz or 14.7 kHz
              2. 8.3.7.1.7.1.2 Sampling Rate: 24 kHz or 22.05 kHz
              3. 8.3.7.1.7.1.3 Sampling Rate: 32 kHz or 29.4 kHz
              4. 8.3.7.1.7.1.4 Sampling Rate: 48 kHz or 44.1 kHz
              5. 8.3.7.1.7.1.5 Sampling Rate: 96 kHz or 88.2 kHz
      8. 8.3.8 Interrupts, Status, and Digital I/O Pin Multiplexing
      9. 8.3.9 Programmable Channel Phase Calibration
    4. 8.4 Device Functional Modes
    5. 8.5 Register Maps
      1. 8.5.1 VEGA Registers
      2. 8.5.2 TAA5212 Registers
      3. 8.5.3 TAA5212 Registers
    6. 8.6 Feature Description
    7. 8.7 Device Functional Modes
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Application
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Performance Plots
      5. 9.2.5 What to Do and What Not to Do
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
Programmable Digital Biquad Filters

The device supports up to 12 programmable digital biquad filters available for ADC signal chain limited to 3/channel. These highly efficient filters achieve the desired frequence response. The TAA5212 also supports on the fly programmable Biquad filters for two channel record use case. In digital signal processing, a digital biquad filter is a second-order, recursive linear filter with two poles and two zeros. Equation 2 gives the transfer function of each biquad filter:

Equation 2. GUID-BC2B8BC9-15A8-4F51-BCDC-655425304DBE-low.gif

The frequency response for the biquad filter section with default coefficients is flat at a gain of 0 dB (all-pass filter). The host device can override the frequency response by programming the biquad coefficients to achieve the desired frequency response for a low-pass, high-pass, or any other desired frequency shaping. The programmable coefficients for the mixer operation are located in the Programmable Coefficient Registers: Page = 0x02 and Programmable Coefficient Registers: Page = 0x03 sections. If biquad filtering is required, then the host device must write these coefficients values before powering up any ADC channels for recording. In two channel use case, the TAA5212 also supports on the fly programmable filters. In this case, Device uses two banks of filters for one channel with a switch bit to perform the switch from one filter bank to the other. As described in Table 8-17, these biquad filters can be allocated for each output channel based on the ADC_DSP_BQ_CFG[1:0] register setting of P0_R114. By setting BIQUAD_CFG[1:0] to 2'b00, the biquad filtering for all record channels is disabled and the host device can choose this setting if no additional filtering is required for the system application. See the TAC5212 Programmable Biquad Filter Configuration and Applications application report for further details.

Table 8-17 Biquad Filter Allocation to the Record Output Channel
PROGRAMMABLE BIQUAD FILTERRECORD OUTPUT CHANNEL ALLOCATION USING P0_R114_D[3:2] REGISTER SETTING
ADC_DSP_BQ_CFG[1:0] = 2'b01
(1 Biquad per Channel)
ADC_DSP_BQ_CFG[1:0] = 2'b10 (Default)
(2 Biquads per Channel)
ADC_DSP_BQ_CFG[1:0] = 2'b11
(3 Biquads per Channel)
Biquad filter 1Allocated to output channel 1Allocated to output channel 1Allocated to output channel 1
Biquad filter 2Allocated to output channel 2Allocated to output channel 2Allocated to output channel 2
Biquad filter 3Allocated to output channel 3Allocated to output channel 3Allocated to output channel 3
Biquad filter 4Allocated to output channel 4Allocated to output channel 4Allocated to output channel 4
Biquad filter 5 Not usedAllocated to output channel 1Allocated to output channel 1
Biquad filter 6Not usedAllocated to output channel 2Allocated to output channel 2
Biquad filter 7 Not usedAllocated to output channel 3Allocated to output channel 3
Biquad filter 8Not usedAllocated to output channel 4Allocated to output channel 4
Biquad filter 9 Not used Not usedAllocated to output channel 1
Biquad filter 10 Not usedNot usedAllocated to output channel 2
Biquad filter 11 Not used Not usedAllocated to output channel 3
Biquad filter 12 Not used Not usedAllocated to output channel 4

Table 8-18 shows the biquad filter coefficients mapping to the register space.

Table 8-18 Biquad Filter Coefficients Register Mapping
PROGRAMMABLE BIQUAD FILTERBIQUAD FILTER COEFFICIENTS REGISTER MAPPINGPROGRAMMABLE BIQUAD FILTERBIQUAD FILTER COEFFICIENTS REGISTER MAPPING
Biquad filter 1P8_R8-R27Biquad filter 7P9_R8-R27
Biquad filter 2P8_R28-R47Biquad filter 8P9_R28-R47
Biquad filter 3P8_R48-R67Biquad filter 9P9_R48-R67
Biquad filter 4P8_R68-R87Biquad filter 10P9_R68-R87
Biquad filter 5P8_R88-R107Biquad filter 11P9_R88-R107
Biquad filter 6P8_R108-R127Biquad filter 12P9_R108-R127