SLASF30 Data sheet

SLASF30 January 2022 TAA5212

ADVANCE INFORMATION

Package Options

Mechanical Data (Package|Pins)

RGE|24
- MPQF124G

Thermal pad, mechanical data (Package|Pins)

Orderable Information

slasf30_oa

8.5.3 TAA5212 Registers

Table 8-139 lists the memory-mapped registers for the TAA5212 registers. All register offset addresses not listed in Table 8-139 should be considered as reserved locations and the register contents should not be modified.

Table 8-139 TAA5212 Registers

Address	Acronym	Register Name	Reset Value	Section
0x0	PAGE_CFG	Device page register	0x00	PAGE_CFG Register (Address = 0x0) [Reset = 0x00]
0x1A	SASI_CFG0	Secondary ASI configuration register 0	0x30	SASI_CFG0 Register (Address = 0x1A) [Reset = 0x30]
0x1B	SASI_TX_CFG0	SASI TX configuration register 0	0x00	SASI_TX_CFG0 Register (Address = 0x1B) [Reset = 0x00]
0x1C	SASI_TX_CFG1	SASI TX configuration register 1	0x00	SASI_TX_CFG1 Register (Address = 0x1C) [Reset = 0x00]
0x1D	SASI_TX_CFG2	SASI TX configuration register 2	0x00	SASI_TX_CFG2 Register (Address = 0x1D) [Reset = 0x00]
0x1E	SASI_TX_CH1_CFG	SASI TX Channel 1 configuration register	0x00	SASI_TX_CH1_CFG Register (Address = 0x1E) [Reset = 0x00]
0x1F	SASI_TX_CH2_CFG	SASI TX Channel 2 configuration register	0x01	SASI_TX_CH2_CFG Register (Address = 0x1F) [Reset = 0x01]
0x20	SASI_TX_CH3_CFG	SASI TX Channel 3 configuration register	0x02	SASI_TX_CH3_CFG Register (Address = 0x20) [Reset = 0x02]
0x21	SASI_TX_CH4_CFG	SASI TX Channel 4 configuration register	0x03	SASI_TX_CH4_CFG Register (Address = 0x21) [Reset = 0x03]
0x22	SASI_TX_CH5_CFG	SASI TX Channel 5 configuration register	0x04	SASI_TX_CH5_CFG Register (Address = 0x22) [Reset = 0x04]
0x23	SASI_TX_CH6_CFG	SASI TX Channel 6 configuration register	0x05	SASI_TX_CH6_CFG Register (Address = 0x23) [Reset = 0x05]
0x24	SASI_TX_CH7_CFG	SASI TX Channel 7 configuration register	0x06	SASI_TX_CH7_CFG Register (Address = 0x24) [Reset = 0x06]
0x26	SASI_RX_CFG0	SASI RX configuration register 0	0x00	SASI_RX_CFG0 Register (Address = 0x26) [Reset = 0x00]
0x32	CLK_CFG12	Clock configuration register 12	0x00	CLK_CFG12 Register (Address = 0x32) [Reset = 0x00]
0x33	CLK_CFG13		0x00	CLK_CFG13 Register (Address = 0x33) [Reset = 0x00]
0x34	CLK_CFG14	Clock configuration register 14	0x10	CLK_CFG14 Register (Address = 0x34) [Reset = 0x10]
0x35	CLK_CFG15	Clock configuration register 15	0x01	CLK_CFG15 Register (Address = 0x35) [Reset = 0x01]
0x36	CLK_CFG16	Clock configuration register 16	0x00	CLK_CFG16 Register (Address = 0x36) [Reset = 0x00]
0x37	CLK_CFG17	Clock configuration register 17	0x00	CLK_CFG17 Register (Address = 0x37) [Reset = 0x00]
0x38	CLK_CFG18	Clock configuration register 18	0x08	CLK_CFG18 Register (Address = 0x38) [Reset = 0x08]
0x39	CLK_CFG19	Clock configuration register 19	0x20	CLK_CFG19 Register (Address = 0x39) [Reset = 0x20]
0x3A	CLK_CFG20	Clock configuration register 20	0x04	CLK_CFG20 Register (Address = 0x3A) [Reset = 0x04]
0x3C	CLK_CFG22	Clock configuration register 18	0x01	CLK_CFG22 Register (Address = 0x3C) [Reset = 0x01]
0x3D	CLK_CFG23	Clock configuration register 18	0x01	CLK_CFG23 Register (Address = 0x3D) [Reset = 0x01]
0x3E	CLK_CFG24	Clock configuration register 21	0x01	CLK_CFG24 Register (Address = 0x3E) [Reset = 0x01]
0x44	CLK_CFG30		0x00	CLK_CFG30 Register (Address = 0x44) [Reset = 0x00]
0x45	CLK_CFG31		0x00	CLK_CFG31 Register (Address = 0x45) [Reset = 0x00]
0x46	CLKOUT_CFG1	CLKOUT configuration register 1	0x00	CLKOUT_CFG1 Register (Address = 0x46) [Reset = 0x00]
0x47	CLKOUT_CFG2	CLKOUT configuration register 2	0x01	CLKOUT_CFG2 Register (Address = 0x47) [Reset = 0x01]
0x49	SARCLK_CFG1	SAR clock configuration register 1	0x00	SARCLK_CFG1 Register (Address = 0x49) [Reset = 0x00]
0x5B	ADC_OVRLD_FLAG		0x00	ADC_OVRLD_FLAG Register (Address = 0x5B) [Reset = 0x00]

8.5.3.1 PAGE_CFG Register (Address = 0x0) [Reset = 0x00]

PAGE_CFG is shown in Table 8-140.

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The device memory map is divided into pages. This register sets the page.

Table 8-140 PAGE_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	PAGE[7:0]	R/W	00000000b	These bits set the device page. 0d = Page 0 1d = Page 1 2d to 254d = Page 2 to page 254 respectively 255d = Page 255

8.5.3.2 SASI_CFG0 Register (Address = 0x1A) [Reset = 0x30]

SASI_CFG0 is shown in Table 8-141.

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This register is the ASI configuration register 0.

Table 8-141 SASI_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	SASI_FORMAT[1:0]	R/W	00b	Secondary ASI protocol format. 0d = TDM mode 1d = I²S mode 2d = LJ (left-justified) mode 3d = Reserved; Don't use
5-4	SASI_WLEN[1:0]	R/W	11b	Secondary ASI word or slot length. 0d = 16 bits (Recommended this setting to be used with 10-kΩ input impedance configuration) 1d = 20 bits 2d = 24 bits 3d = 32 bits
3	SASI_FSYNC_POL	R/W	0b	ASI FSYNC polarity (for SASI protocol only). 0d = Default polarity as per standard protocol 1d = Inverted polarity with respect to standard protocol
2	SASI_BCLK_POL	R/W	0b	ASI BCLK polarity (for SASI protocol only). 0d = Default polarity as per standard protocol 1d = Inverted polarity with respect to standard protocol
1	SASI_BUS_ERR	R/W	0b	ASI bus error detection. 0d = Enable bus error detection 1d = Disable bus error detection
0	SASI_BUS_ERR_RCOV	R/W	0b	ASI bus error auto resume. 0d = Enable auto resume after bus error recovery 1d = Disable auto resume after bus error recovery and remain powered down until host configures the device

8.5.3.3 SASI_TX_CFG0 Register (Address = 0x1B) [Reset = 0x00]

SASI_TX_CFG0 is shown in Table 8-142.

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This register is the SASI TX configuration register 0.

Table 8-142 SASI_TX_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	SASI_TX_EDGE	R/W	0b	Secondary ASI data output (on the primary and secondary data pin) transmit edge. 0d = Default edge as per the protocol configuration setting in SASI_BCLK_POL 1d = Inverted following edge (half cycle delay) with respect to the default edge setting
6	SASI_TX_FILL	R/W	0b	Secondary ASI data output (on the primary and secondary data pin) for any unused cycles 0d = Always transmit 0 for unused cycles 1d = Always use Hi-Z for unused cycles
5	SASI_TX_LSB	R/W	0b	Secondary ASI data output (on the primary and secondary data pin) for LSB transmissions. 0d = Transmit the LSB for a full cycle 1d = Transmit the LSB for the first half cycle and Hi-Z for the second half cycle
4-3	SASI_TX_KEEPER[1:0]	R/W	00b	Secondary ASI data output (on the primary and secondary data pin) bus keeper. 0d = Bus keeper is always disabled 1d = Bus keeper is always enabled 2d = Bus keeper is enabled during LSB transmissions only for one cycle 3d = Bus keeper is enabled during LSB transmissions only for one and half cycles
2	SASI_TX_USE_INT_FSYNC	R/W	0b	Secondary ASI uses internal FSYNC for output data generation in controller mode configuration as applicable. 0d = Use external FSYNC for ASI protocol data generation 1d = Use internal FSYNC for ASI protocol data generation
1	SASI_TX_USE_INT_BCLK	R/W	0b	Secondary ASI uses internal BCLK for output data generation in controller mode configuration. 0d = Use external BCLK for ASI protocol data generation 1d = Use internal BCLK for ASI protocol data generation
0	SASI_TDM_PULSE_WIDTH	R/W	0b	Secondary ASI fsync pulse width in TDM format. 0d = Fsync pulse is 1 bclk period wide 1d = Fsync pulse is 2 bclk period wide

8.5.3.4 SASI_TX_CFG1 Register (Address = 0x1C) [Reset = 0x00]

SASI_TX_CFG1 is shown in Table 8-143.

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This register is the SASI TX configuration register 1.

Table 8-143 SASI_TX_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-5	RESERVED	R	000b	Reserved bits; Write only reset value
4-0	SASI_TX_OFFSET[4:0]	R/W	00000b	Secondary ASI output data MSB slot 0 offset (on the primary and secondary data pin). 0d = ASI data MSB location has no offset and is as per standard protocol 1d = ASI data MSB location (TDM mode is slot 0 or I²S, LJ mode is the left and right slot 0) offset of one BCLK cycle with respect to standard protocol 2d = ASI data MSB location (TDM mode is slot 0 or I²S, LJ mode is the left and right slot 0) offset of two BCLK cycles with respect to standard protocol 3d to 30d = ASI data MSB location (TDM mode is slot 0 or I²S, LJ mode is the left and right slot 0) offset assigned as per configuration 31d = ASI data MSB location (TDM mode is slot 0 or I²S, LJ mode is the left and right slot 0) offset of 31 BCLK cycles with respect to standard protocol

8.5.3.5 SASI_TX_CFG2 Register (Address = 0x1D) [Reset = 0x00]

SASI_TX_CFG2 is shown in Table 8-144.

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This register is the SASI TX configuration register 2.

Table 8-144 SASI_TX_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	SASI_TX_CH8_SEL	R/W	0b	Secondary ASI output channel 8 select. 0d = Secondary ASI channel 8 output is on DOUT 1d = Secondary ASI channel 8 output is on DOUT2
6	SASI_TX_CH7_SEL	R/W	0b	Secondary ASI output channel 7 select. 0d = Secondary ASI channel 7 output is on DOUT 1d = Secondary ASI channel 7 output is on DOUT2
5	SASI_TX_CH6_SEL	R/W	0b	Secondary ASI output channel 6 select. 0d = Secondary ASI channel 6 output is on DOUT 1d = Secondary ASI channel 6 output is on DOUT2
4	SASI_TX_CH5_SEL	R/W	0b	Secondary ASI output channel 5 select. 0d = Secondary ASI channel 5 output is on DOUT 1d = Secondary ASI channel 5 output is on DOUT2
3	SASI_TX_CH4_SEL	R/W	0b	Secondary ASI output channel 4 select. 0d = Secondary ASI channel 4 output is on DOUT 1d = Secondary ASI channel 4 output is on DOUT2
2	SASI_TX_CH3_SEL	R/W	0b	Secondary ASI output channel 3 select. 0d = Secondary ASI channel 3 output is on DOUT 1d = Secondary ASI channel 3 output is on DOUT2
1	SASI_TX_CH2_SEL	R/W	0b	Secondary ASI output channel 2 select. 0d = Secondary ASI channel 2 output is on DOUT 1d = Secondary ASI channel 2 output is on DOUT2
0	SASI_TX_CH1_SEL	R/W	0b	Secondary ASI output channel 1 select. 0d = Secondary ASI channel 1 output is on DOUT 1d = Secondary ASI channel 1 output is on DOUT2

8.5.3.6 SASI_TX_CH1_CFG Register (Address = 0x1E) [Reset = 0x00]

SASI_TX_CH1_CFG is shown in Table 8-145.

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This register is the SASI TX Channel 1 configuration register.

Table 8-145 SASI_TX_CH1_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	00b	Reserved bits; Write only reset value
5	SASI_TX_CH1_CFG	R/W	0b	Secondary ASI output channel 1 configuration. 0d = Secondary ASI channel 1 output is in a tri-state condition 1d = Secondary ASI channel 1 output corresponds to ADC Channel 1 data
4-0	SASI_TX_CH1_SLOT_NUM[4:0]	R/W	00000b	Secondary ASI output channel 1 slot assignment. 0d = TDM is slot 0 or I²S, LJ is left slot 0 1d = TDM is slot 1 or I²S, LJ is left slot 1 2d to 14d = Slot assigned as per configuration 15d = TDM is slot 15 or I²S, LJ is left slot 15 16d = TDM is slot 16 or I²S, LJ is right slot 0 17d = TDM is slot 17 or I²S, LJ is right slot 1 18d to 30d = Slot assigned as per configuration 31d = TDM is slot 31 or I²S, LJ is right slot 15

8.5.3.7 SASI_TX_CH2_CFG Register (Address = 0x1F) [Reset = 0x01]

SASI_TX_CH2_CFG is shown in Table 8-146.

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This register is the SASI TX Channel 2 configuration register.

Table 8-146 SASI_TX_CH2_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	00b	Reserved bits; Write only reset value
5	SASI_TX_CH2_CFG	R/W	0b	Secondary ASI output channel 2 configuration. 0d = Secondary ASI channel 2 output is in a tri-state condition 1d = Secondary ASI channel 2 output corresponds to ADC Channel 2 data
4-0	SASI_TX_CH2_SLOT_NUM[4:0]	R/W	00001b	Secondary ASI output channel 2 slot assignment. 0d = TDM is slot 0 or I²S, LJ is left slot 0 1d = TDM is slot 1 or I²S, LJ is left slot 1 2d to 14d = Slot assigned as per configuration 15d = TDM is slot 15 or I²S, LJ is left slot 15 16d = TDM is slot 16 or I²S, LJ is right slot 0 17d = TDM is slot 17 or I²S, LJ is right slot 1 18d to 30d = Slot assigned as per configuration 31d = TDM is slot 31 or I²S, LJ is right slot 15

8.5.3.8 SASI_TX_CH3_CFG Register (Address = 0x20) [Reset = 0x02]

SASI_TX_CH3_CFG is shown in Table 8-147.

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This register is the SASI TX Channel 3 configuration register.

Table 8-147 SASI_TX_CH3_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0b	Reserved bit; Write only reset value
6-5	SASI_TX_CH3_CFG[1:0]	R/W	00b	Secondary ASI output channel 3 configuration. 0d = Secondary ASI channel 3 output is in a tri-state condition 1d = Secondary ASI channel 3 output corresponds to ADC Channel 3 data 2d = Secondary ASI channel 3 output corresponds to VBAT data 3d = Reserved
4-0	SASI_TX_CH3_SLOT_NUM[4:0]	R/W	00010b	Secondary ASI output channel 3 slot assignment. 0d = TDM is slot 0 or I²S, LJ is left slot 0 1d = TDM is slot 1 or I²S, LJ is left slot 1 2d to 14d = Slot assigned as per configuration 15d = TDM is slot 15 or I²S, LJ is left slot 15 16d = TDM is slot 16 or I²S, LJ is right slot 0 17d = TDM is slot 17 or I²S, LJ is right slot 1 18d to 30d = Slot assigned as per configuration 31d = TDM is slot 31 or I²S, LJ is right slot 15

8.5.3.9 SASI_TX_CH4_CFG Register (Address = 0x21) [Reset = 0x03]

SASI_TX_CH4_CFG is shown in Table 8-148.

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This register is the SASI TX Channel 4 configuration register.

Table 8-148 SASI_TX_CH4_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0b	Reserved bit; Write only reset value
6-5	SASI_TX_CH4_CFG[1:0]	R/W	00b	Secondary ASI output channel 4 configuration. 0d = Secondary ASI channel 4 output is in a tri-state condition 1d = Secondary ASI channel 4 output corresponds to ADC Channel 4 data 2d = Secondary ASI channel 4 output corresponds to TEMP data 3d = Reserved
4-0	SASI_TX_CH4_SLOT_NUM[4:0]	R/W	00011b	Secondary ASI output channel 4 slot assignment. 0d = TDM is slot 0 or I²S, LJ is left slot 0 1d = TDM is slot 1 or I²S, LJ is left slot 1 2d to 14d = Slot assigned as per configuration 15d = TDM is slot 15 or I²S, LJ is left slot 15 16d = TDM is slot 16 or I²S, LJ is right slot 0 17d = TDM is slot 17 or I²S, LJ is right slot 1 18d to 30d = Slot assigned as per configuration 31d = TDM is slot 31 or I²S, LJ is right slot 15

8.5.3.10 SASI_TX_CH5_CFG Register (Address = 0x22) [Reset = 0x04]

SASI_TX_CH5_CFG is shown in Table 8-149.

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This register is the SASI TX Channel 5 configuration register.

Table 8-149 SASI_TX_CH5_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0b	Reserved bit; Write only reset value
6-5	SASI_TX_CH5_CFG[1:0]	R/W	00b	Secondary ASI output channel 5 configuration. 0d = Secondary ASI channel 5 output is in a tri-state condition 1d = Secondary ASI channel 5 output corresponds to ASI Input Channel 1 loopback data Dont use Dont use
4-0	SASI_TX_CH5_SLOT_NUM[4:0]	R/W	00100b	Secondary ASI output channel 5 slot assignment. 0d = TDM is slot 0 or I²S, LJ is left slot 0 1d = TDM is slot 1 or I²S, LJ is left slot 1 2d to 14d = Slot assigned as per configuration 15d = TDM is slot 15 or I²S, LJ is left slot 15 16d = TDM is slot 16 or I²S, LJ is right slot 0 17d = TDM is slot 17 or I²S, LJ is right slot 1 18d to 30d = Slot assigned as per configuration 31d = TDM is slot 31 or I²S, LJ is right slot 15

8.5.3.11 SASI_TX_CH6_CFG Register (Address = 0x23) [Reset = 0x05]

SASI_TX_CH6_CFG is shown in Table 8-150.

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This register is the SASI TX Channel 6 configuration register.

Table 8-150 SASI_TX_CH6_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0b	Reserved bit; Write only reset value
6-5	SASI_TX_CH6_CFG[1:0]	R/W	00b	Secondary ASI output channel 6 configuration. 0d = Secondary ASI channel 6 output is in a tri-state condition 1d = Secondary ASI channel 6 output corresponds to ASI Input Channel 2 loopback data Dont use Dont use
4-0	SASI_TX_CH6_SLOT_NUM[4:0]	R/W	00101b	Secondary ASI output channel 6 slot assignment. 0d = TDM is slot 0 or I²S, LJ is left slot 0 1d = TDM is slot 1 or I²S, LJ is left slot 1 2d to 14d = Slot assigned as per configuration 15d = TDM is slot 15 or I²S, LJ is left slot 15 16d = TDM is slot 16 or I²S, LJ is right slot 0 17d = TDM is slot 17 or I²S, LJ is right slot 1 18d to 30d = Slot assigned as per configuration 31d = TDM is slot 31 or I²S, LJ is right slot 15

8.5.3.12 SASI_TX_CH7_CFG Register (Address = 0x24) [Reset = 0x06]

SASI_TX_CH7_CFG is shown in Table 8-151.

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This register is the SASI TX Channel 7 configuration register.

Table 8-151 SASI_TX_CH7_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0b	Reserved bit; Write only reset value
6-5	SASI_TX_CH7_CFG[1:0]	R/W	00b	Secondary ASI output channel 7 configuration. 0d = Secondary ASI channel 7 output is in a tri-state condition 1d = Secondary ASI channel 7 output corresponds to {VBAT_WLby2, TEMP_WLby2} Dont use Dont use
4-0	SASI_TX_CH7_SLOT_NUM[4:0]	R/W	00110b	Secondary ASI output channel 7 slot assignment. 0d = TDM is slot 0 or I²S, LJ is left slot 0 1d = TDM is slot 1 or I²S, LJ is left slot 1 2d to 14d = Slot assigned as per configuration 15d = TDM is slot 15 or I²S, LJ is left slot 15 16d = TDM is slot 16 or I²S, LJ is right slot 0 17d = TDM is slot 17 or I²S, LJ is right slot 1 18d to 30d = Slot assigned as per configuration 31d = TDM is slot 31 or I²S, LJ is right slot 15

8.5.3.13 SASI_RX_CFG0 Register (Address = 0x26) [Reset = 0x00]

SASI_RX_CFG0 is shown in Table 8-152.

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This register is the SASI RX configuration register 0.

Table 8-152 SASI_RX_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	SASI_RX_EDGE	R/W	0b	Secondary ASI data input (on the primary and secondary data pin) receive edge. 0d = Default edge as per the protocol configuration setting in bit 2 (BCLK_POL) 1d = Inverted following edge (half cycle delay) with respect to the default edge setting
6	SASI_RX_USE_INT_FSYNC	R/W	0b	Secondary ASI uses internal FSYNC for input data latching in controller mode configuration as applicable. 0d = Use external FSYNC for ASI protocol data latching 1d = Use internal FSYNC for ASI protocol data latching
5	SASI_RX_USE_INT_BCLK	R/W	0b	Secondary ASI uses internal BCLK for input data latching in controller mode configuration. 0d = Use external BCLK for ASI protocol data latching 1d = Use internal BCLK for ASI protocol data latching
4-0	SASI_RX_OFFSET[4:0]	R/W	00000b	Secondary ASI data input MSB slot 0 offset (on the primary and secondary data pin). 0d = ASI data MSB location has no offset and is as per standard protocol 1d = ASI data MSB location (TDM mode is slot 0 or I²S, LJ mode is the left and right slot 0) offset of one BCLK cycle with respect to standard protocol 2d = ASI data MSB location (TDM mode is slot 0 or I²S, LJ mode is the left and right slot 0) offset of two BCLK cycles with respect to standard protocol 3d to 30d = ASI data MSB location (TDM mode is slot 0 or I²S, LJ mode is the left and right slot 0) offset assigned as per configuration 31d = ASI data MSB location (TDM mode is slot 0 or I²S, LJ mode is the left and right slot 0) offset of 31 BCLK cycles with respect to standard protocol

8.5.3.14 CLK_CFG12 Register (Address = 0x32) [Reset = 0x00]

CLK_CFG12 is shown in Table 8-153.

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This register is the clock configuration register 12.

Table 8-153 CLK_CFG12 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	PDIV_CLKSRC_SEL[1:0]	R/W	00b	Source clock selection for PLL PDIV Divider. 0d = PLL_PDIV_IN_CLK is Primary ASI BCLK 1d = PLL_PDIV_IN_CLK is Secondary ASI BCLK 2d = PLL_PDIV_IN_CLK is CCLK 3d = PLL_PDIV_IN_CLK is internal Oscillator Clock
5-3	PASI_BCLK_DIV_CLK_SEL[2:0]	R/W	000b	Primary ASI BCLK divider clock source selection. 0d = Primary ASI BCLK divider clock source is PLL output 1d = Reserved 2d = Primary ASI BCLK divider clock source is secondary ASI BCLK 3d = Primary ASI BCLK divider clock source is CCLK 4d = Primary ASI BCLK divider clock source is internal oscillator clock 5d = Primary ASI BCLK divider clock source is DSP clock 6d to 7d = Reserved
2-0	RESERVED	R	000b	Reserved bits; Write only reset value

8.5.3.15 CLK_CFG13 Register (Address = 0x33) [Reset = 0x00]

CLK_CFG13 is shown in Table 8-154.

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Table 8-154 CLK_CFG13 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0b	Reserved bit; Write only reset value
6-4	SASI_BCLK_DIV_CLK_SEL[2:0]	R/W	000b	Secondaary ASI BCLK divider clock source selection. 0d = Secondaary ASI BCLK divider clock source is PLL output 1d = Secondaary ASI BCLK divider clock source is primary ASI BCLK 2d = Reserved 3d = Secondaary ASI BCLK divider clock source is CCLK 4d = Secondaary ASI BCLK divider clock source is internal oscillator clock 5d = Secondaary ASI BCLK divider clock source is DSP clock 6d to 7d = Reserved
3-0	RESERVED	R	0000b	Reserved bits; Write only reset value

8.5.3.16 CLK_CFG14 Register (Address = 0x34) [Reset = 0x10]

CLK_CFG14 is shown in Table 8-155.

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This register is the clock configuration register 14.

Table 8-155 CLK_CFG14 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	DIG_NM_DIV_CLK_SRC_SEL[1:0]	R/W	00b	Source clock selection for DIG NMDIV CLK clock. 0d = DIG NM divider input clock is Primary ASI BCLK 1d = DIG NM divider input clock is Secondary ASI BCLK 2d = DIG NM divider input clock is CCLK 3d = DIG NM divider input clock is internal oscillator clock
5-4	ANA_NM_DIV_CLK_SRC_SEL[1:0]	R/W	01b	Source clock selection for NMDIV CLK clock. 0d = NM divider input clock is PLL Output 1d = NM divider input clock is PLL Output 2d = NM divider input clock is DIG NM Divider Clock Source 3d = NM divider input clock is Primary ASI BCLK (Low Jitter Path)
3-2	RESERVED	R/W	00b	Reserved bits; Write only reset values
1-0	RESERVED	R/W	00b	Reserved bits; Write only reset values

8.5.3.17 CLK_CFG15 Register (Address = 0x35) [Reset = 0x01]

CLK_CFG15 is shown in Table 8-156.

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This register is the clock configuration register 15.

Table 8-156 CLK_CFG15 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	PLL_PDIV[7:0]	R/W	00000001b	PLL pre-scaler P-divider value (Don't care when auto detection is enabled) 0d = PLL PDIV value is 256 1d = PLL PDIV value is 1 2d = PLL PDIV value is 2 3d to 254d = PLL PDIV value is as per configuration 255d = PLL PDIV value is 255

8.5.3.18 CLK_CFG16 Register (Address = 0x36) [Reset = 0x00]

CLK_CFG16 is shown in Table 8-157.

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This register is the clock configuration register 16.

Table 8-157 CLK_CFG16 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	PLL_JMUL_MSB	R/W	0b	PLL integer portion J-multiplier value MSB bit. (Don't care when auto detection is enabled)
6	PLL_DIV_CLK_DIG_BY_2	R/W	0b	PLL DIV clock divide by 2 configuration 0d = No divide/2 inside PLL 1d = PLL does a divide/2
5-0	PLL_DMUL_MSB[5:0]	R/W	000000b	PLL fractional portion D-multiplier value MSB bits. (Don't care when auto detection is enabled)

8.5.3.19 CLK_CFG17 Register (Address = 0x37) [Reset = 0x00]

CLK_CFG17 is shown in Table 8-158.

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This register is the clock configuration register 17.

Table 8-158 CLK_CFG17 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	PLL_DMUL_LSB[7:0]	R/W	00000000b	PLL fractional portion D-multiplier value LSB byte. Above D-multiplier value MSB bits (PLL_DMUL_MSB) along with this LSB byte (PLL_DMUL_LSB) is concatenated to determine final D-multiplier value. (Don't care when auto detection is enabled) 0d = PLL DMUL value is 0 1d = PLL DMUL value is 1 2d = PLL DMUL value is 2 3d to 9998d = PLL JMUL value is as per configuration 9999d = PLL JMUL value is 9999 10000d to 16383d = Reserved; Don't use

8.5.3.20 CLK_CFG18 Register (Address = 0x38) [Reset = 0x08]

CLK_CFG18 is shown in Table 8-159.

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This register is the clock configuration register 18.

Table 8-159 CLK_CFG18 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	PLL_JMUL_LSB[7:0]	R/W	00001000b	PLL integer portion J-multiplier value LSB byte. Above J-multiplier value MSB bit (PLL_JMUL_MSB) along with this LSB byte (PLL_JMUL_LSB) is concatenated to determine fianl J-multiplier value. (Don't care when auto detection is enabled) 0d = Reserved; Don't use 1d = PLL JMUL value is 1 2d = PLL JMUL value is 2 3d to 510d = PLL JMUL value is as per configuration 511d = PLL JMUL value is 511

8.5.3.21 CLK_CFG19 Register (Address = 0x39) [Reset = 0x20]

CLK_CFG19 is shown in Table 8-160.

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This register is the clock configuration register 19.

Table 8-160 CLK_CFG19 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-5	NDIV[2:0]	R/W	001b	NDIV divider value. (Don't care when auto detection is enabled) 0d = NDIV value is 8 1d = NDIV value is 1 2d = NDIV value is 2 3d to 6d = NDIV value is as per configuration 7d = NDIV value is 7
4-2	PDM_DIV[2:0]	R/W	000b	PDM divider value. (Don't care when auto detection is enabled) 0d = PDM_DIV value is 1 1d = PDM_DIV value is 2 2d = PDM_DIV value is 4 3d = PDM_DIV value is 8 4d = PDM_DIV value is 16 5d-7d Reserved
1-0	RESERVED	R/W	00b	Reserved bits; Write only reset values

8.5.3.22 CLK_CFG20 Register (Address = 0x3A) [Reset = 0x04]

CLK_CFG20 is shown in Table 8-161.

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This register is the clock configuration register 20.

Table 8-161 CLK_CFG20 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-2	MDIV[5:0]	R/W	000001b	MDIV divider value. (Don't care when auto detection is enabled) 0d = MDIV value is 64 1d = MDIV value is 1 2d = MDIV value is 2 3d to 62d = MDIV value is as per configuration 63d = MDIV value is 63
1-0	DIG_ADC_MODCLK_DIV[1:0]	R/W	00b	ADC modulator clock divider value. (Don't care when auto detection is enabled) 0d = DIG_ADC_MODCLK_DIV value is 1 1d = DIG_ADC_MODCLK_DIV value is 2 2d = DIG_ADC_MODCLK_DIV value is 4 3d = Reserved

8.5.3.23 CLK_CFG22 Register (Address = 0x3C) [Reset = 0x01]

CLK_CFG22 is shown in Table 8-162.

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This register is the clock configuration register 18.

Table 8-162 CLK_CFG22 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	PASI_BDIV_LSB[7:0]	R/W	00000001b	Secondary ASI BCLK divider value. (Don't care when auto detection is enabled) 0d = SASI BCLK divider value is 512 1d = SASI BCLK divider value is 1 2d = SASI BCLK divider value is 2 3d to 62d = SASI BCLK divider value is as per configuration 63d = SASI BCLK divider value is 511

8.5.3.24 CLK_CFG23 Register (Address = 0x3D) [Reset = 0x01]

CLK_CFG23 is shown in Table 8-163.

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This register is the clock configuration register 18.

Table 8-163 CLK_CFG23 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	SASI_BDIV_LSB[7:0]	R/W	00000001b	Secondary ASI BCLK divider value. (Don't care when auto detection is enabled) 0d = SASI BCLK divider value is 512 1d = SASI BCLK divider value is 1 2d = SASI BCLK divider value is 2 3d to 62d = SASI BCLK divider value is as per configuration 63d = SASI BCLK divider value is 511

8.5.3.25 CLK_CFG24 Register (Address = 0x3E) [Reset = 0x01]

CLK_CFG24 is shown in Table 8-164.

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This register is the clock configuration register 21.

Table 8-164 CLK_CFG24 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	00b	Reserved bits; Write only reset value
5-0	ANA_NM_DIV[5:0]	R/W	000001b	Analog N-M DIV divider value. (Don't care when auto detection is enabled) 0d = ANA_NM_DIV value is 64 1d = ANA_NM_DIV value is 1 2d = ANA_NM_DIV value is 2 3d to 62d = ANA_NM_DIV value is as per configuration 63d = NDIV value is 63

8.5.3.26 CLK_CFG30 Register (Address = 0x44) [Reset = 0x00]

CLK_CFG30 is shown in Table 8-165.

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Table 8-165 CLK_CFG30 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-3	RESERVED	R	00000b	Reserved bits; Write only reset value
2	NDIV_EN	R/W	0b	NDIV divider enable 0d = divider disabled 1d = divider enabled
1	MDIV_EN	R/W	0b	MDIV divider enable 0d = divider disabled 1d = divider enabled
0	PDM_DIV_EN	R/W	0b	PDM divider enable 0d = divider disabled 1d = divider enabled

8.5.3.27 CLK_CFG31 Register (Address = 0x45) [Reset = 0x00]

CLK_CFG31 is shown in Table 8-166.

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Table 8-166 CLK_CFG31 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R/W	0b	Reserved bit; Write only reset value
6	DIG_ADC_MODCLK_DIV_EN	R/W	0b	ADC MODCLK divider enable 0d = divider disabled 1d = divider enabled
5	RESERVED	R/W	0b	Reserved bit; Write only reset value
4	RESERVED	R/W	0b	Reserved bit; Write only reset value
3	PASI_BDIV_EN	R/W	0b	PASI BDIV divider enable 0d = divider disabled 1d = divider enabled
2	SASI_BDIV_EN	R/W	0b	SASI BDIV divider enable 0d = divider disabled 1d = divider enabled
1	PASI_FSYNC_DIV_EN	R/W	0b	PASI FSYNC DIV divider enable 0d = divider disabled 1d = divider enabled
0	SASI_FSYNC_DIV_EN	R/W	0b	SASI FSYNC DIV divider enable 0d = divider disabled 1d = divider enabled

8.5.3.28 CLKOUT_CFG1 Register (Address = 0x46) [Reset = 0x00]

CLKOUT_CFG1 is shown in Table 8-167.

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This register is the CLKOUT configuration register 1.

Table 8-167 CLKOUT_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-3	RESERVED	R	00000b	Reserved bits; Write only reset value
2-0	CLKOUT_CLK_SEL[2:0]	R/W	000b	General Purpose CLKOUT divider clock source selection. 0d = Source clock is PLL output 1d = Source clock is primary ASI BCLK 2d = Source clock is secondary ASI BCLK 3d = Source clock is CCLK 4d = Source clock is internal oscillator clock 5d = Source clock is DSP clock 6d to 7d = Reserved

8.5.3.29 CLKOUT_CFG2 Register (Address = 0x47) [Reset = 0x01]

CLKOUT_CFG2 is shown in Table 8-168.

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This register is the CLKOUT configuration register 2.

Table 8-168 CLKOUT_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	CLKOUT_DIV_EN	R/W	0b	CLKOUT divider enable. 0d = CLKOUT divider disabled 1d = CLKOUT divider enabled
6-0	CLKOUT_DIV[6:0]	R/W	0000001b	CLKOUT DIV divider value. 0d = CLKOUT_DIV value is 128 1d = CLKOUT_DIV value is 1 2d = CLKOUT_DIV value is 2 3d to 126d = CLKOUT_DIV value is as per configuration 127d = CLKOUT_DIV value is 127

8.5.3.30 SARCLK_CFG1 Register (Address = 0x49) [Reset = 0x00]

SARCLK_CFG1 is shown in Table 8-169.

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This register is the SAR clock configuration register 1

Table 8-169 SARCLK_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	SAR_CLK_FREQ_SEL[1:0]	R/W	00b	SAR clock frequency mode 0d = SAR clock frequency is ~6MHz 1d = SAR clock frequency is ~3MHz 2d = SAR clock frequency is ~1.5MHz 3d = SAR clock frequency is ~12MHz (valid only when SAR clock is generated directly using internal oscilator clock
5	SAR_CLK_SRC_AUTO_DIS	R/W	0b	SAR divider source clock auto selection disable 0d = SAR divider source clock auto-selection based on clock detection scheme 1d = SAR divider source clock auto-selection disabled and selected based on BST_CLK_SRC_SEL
4	SAR_CLK_SRC_MANUAL_SEL	R/W	0b	SAR clock source manual selection (don't care in auto mode) 0d = SAR clock generated based on Audio clock available for ADC/DAC 1d = SAR clock generated based on internal oscillator clock
3	SAR_CLK_EN_AUTO_DIS	R/W	0b	SAR divider source clock auto selection disable 0d = SAR divider auto-enabled 1d = SAR divider enabled/disabled based on manual control using BST_CLK_EN
2	SAR_CLK_MANUAL_EN	R/W	0b	SAR divider manual enable (don't care in auto mode) 0d = SAR divider disabled 1d = SAR divider enabled
1-0	SAR_CLK_MANUAL_DIV[1:0]	R/W	00b	SAR divider value (don't care in auto mode) 0d = SAR divider value is 1 1d = SAR divider value is 2 2d = SAR divider value is 4 3d = SAR divider value is 8

8.5.3.31 ADC_OVRLD_FLAG Register (Address = 0x5B) [Reset = 0x00]

ADC_OVRLD_FLAG is shown in Table 8-170.

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Table 8-170 ADC_OVRLD_FLAG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	ADC_CH1_OVRLD_LTCH	R	0b	ADC CH1 OVRLD fault (self clearing bit). 0b = No ADC CH1 OVRLD fault 1b = ADC CH1 OVRLD fault
6	ADC_CH2_OVRLD_LTCH	R	0b	ADC CH2 OVRLD fault (self clearing bit). 0b = No ADC CH2 OVRLD fault 1b = ADC CH2 OVRLD fault
5	ADC_CH1_OVRLD_LIVE	R	0b	ADC CH1 OVRLD fault (self clearing bit). 0b = No ADC CH1 OVRLD fault 1b = ADC CH1 OVRLD fault
4	ADC_CH2_OVRLD_LIVE	R	0b	ADC CH2 OVRLD fault (self clearing bit). 0b = No ADC CH2 OVRLD fault 1b = ADC CH2 OVRLD fault
3-0	RESERVED	R	0000b	Reserved bits; Write only reset value