SLLSEZ1C September   2017  – May 2019 TDP142

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematics
      2.      Display
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Supply Characteristics
    6. 6.6  DC Electrical Characteristics
    7. 6.7  AC Electrical Characteristics
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DisplayPort
      2. 8.3.2 4-level Inputs
      3. 8.3.3 Receiver Linear Equalization
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Configuration in GPIO Mode
      2. 8.4.2 Device Configuration In I2C Mode
      3. 8.4.3 Linear EQ Configuration
      4. 8.4.4 Operation Timing – Power Up
    5. 8.5 Programming
    6. 8.6 Register Maps
      1. 8.6.1 General Register (address = 0x0A) [reset = 00000001]
        1. Table 6. General Registers
      2. 8.6.2 DisplayPort Control/Status Registers (address = 0x10) [reset = 00000000]
        1. Table 7. DisplayPort Control/Status Registers (0x10)
      3. 8.6.3 DisplayPort Control/Status Registers (address = 0x11) [reset = 00000000]
        1. Table 8. DisplayPort Control/Status Registers (0x11)
      4. 8.6.4 DisplayPort Control/Status Registers (address = 0x12) [reset = 00000000]
        1. Table 9. DisplayPort Control/Status Registers (0x12)
      5. 8.6.5 DisplayPort Control/Status Registers (address = 0x13) [reset = 00000000]
        1. Table 10. DisplayPort Control/Status Registers (0x13)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Source Application Implementation
        1. 9.2.1.1 Design Requirement
        2. 9.2.1.2 Detail Design Procedure
      2. 9.2.2 Sink Application Implementation
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.6.2 DisplayPort Control/Status Registers (address = 0x10) [reset = 00000000]

Figure 12. DisplayPort Control/Status Registers (0x10)
7 6 5 4 3 2 1 0
DP1EQ_SEL DP0EQ_SEL
R/W/U R/W/U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 7. DisplayPort Control/Status Registers (0x10)

Bit Field Type Reset Description
7:4 DP1EQ_SEL R/W/U 0000 Field selects between 0 to 14dB of EQ for DP lane 1. When EQ_OVERRIDE = 1’b0, this field reflects the sampled state of DPEQ[1:0] pins. When EQ_OVERRIDE = 1’b1, software can change the EQ setting for DP lane 1 based on value written to this field.
3:0 DP0EQ_SEL R/W/U 0000 Field selects between 0 to 14dB of EQ for DP lane 0. When EQ_OVERRIDE = 1’b0, this field reflects the sampled state of DPEQ[1:0] pins. When EQ_OVERRIDE = 1’b1, software can change the EQ setting for DP lane 0 based on value written to this field.