The THS3215 is well suited for high-speed, low-distortion arbitrary waveform generator (AWG) applications commonly used in laboratory equipment. In this typical application, a high-speed, complementary-current-output DAC is used to drive the D2S. The OPS of the THS3215 easily drives a 50 MHz, 2.5 V_PP signal into a matched 50 Ω load. When a larger output signal is required, consider using the THS3095 as the final driver stage.

A passive RLC filter is commonly used on DAC outputs to reduce the high-frequency content in the DAC steps. The filtering between the DAC output and the input to the D2S reduces higher-order DAC harmonics from feeding into the internal OPS path when the external input path is selected. Feedthrough between the internal and external OPS paths increases with increasing frequency; however, the input filter rolls off the DAC harmonics before the harmonics couple to VOUT (pin 10) through the deselected OPS signal path. Figure 9-2 shows an example of a doubly-terminated differential filter from the DAC to the THS3215 D2S inputs at +IN (pin 2) and –IN (pin 3). The DAC is modeled as two, fixed, 10 mA currents and a differential, ac-current source. The 10 mA dc midscale currents set up the average common-mode voltage at the DAC outputs and D2S inputs at 10 mA × 25 Ω = 0.25 V_CM. The total voltage swing on each DAC output is 0 V to 0.5 V.

Figure 9-2 105 MHz Butterworth Filter Between DAC and D2S Inputs

Some of the guidelines to consider in this filter design are:

1. The filter cutoff is adjusted to hit a standard value in the standard high-frequency, chip inductors kits.
2. The required filter output capacitance is reduced from the design value of 29.4 pF to 27 pF to account for the D2S input capacitance of 2.4 pF, as reported in the D2S Electrical Characteristics table.
3. The capacitor at the DAC output pins must also be reduced by the expected DAC output pin capacitance. The DAC output capacitance is often specified as 5 pF, but is usually much lower. Contact the DAC manufacturer for an accurate value.

Figure 9-3 shows the TINA-simulated filter response for the input-stage filter. The low-frequency 34 dBΩ gain is due to the 50 Ω differential resistance at the DAC output terminals. At 200 MHz, this filter is down 17 dB from the 50 Ω level; it is also very flat through 50 MHz.

Figure 9-3 Simulated, Differential-Input Filter Response

In the example design of Figure 9-1, a 50 MHz, third-order Bessel filter is placed between the D2S output and the external OPS input. Another 25 MHz, third-order Bessel filter is placed at the input of a very-high output-swing THS3095 stage. A double-pole, double-throw (DPDT) relay selects the THS3095 path when the internal OPS path is selected in the THS3215. Figure 9-1 shows this design. The key operational considerations in this design include:

1. When the external input OPS path is selected, the 2 V_PP maximum D2S output swing experiences a 1.55 dB insertion loss from the interstage filter between VO1 (pin 6) and VIN+ (pin 9). A standard value inductor is used and the 464 Ω termination accounts for the internal 18.5 kΩ element. The 10 Ω resistor at VIN+ isolates the OPS input from the 52 pF filter capacitor. To recover the insertion loss and produce a maximum 5 V_PP output, the OPS gain is set to 2.96 V/V. When the interstage filter path is selected, the two DPDT relays pass the OPS output on directly from the 49.9 Ω output matching resistor to V_O. Disable the THS3095 to conserve power.
2. To deliver 20 V_PP at the V_O output, select the THS3095 path. Select the internal OPS path to bypass the 50 MHz filter (1.55 dB insertion loss) in order to give a maximum 5.9 V_PP output at VOUT (pin 11). The two DPDT relays switch position, and the 49.9 Ω at the OPS output becomes part of the 25 MHz, third-order Bessel filter into the THS3095 stage. This filter has a 1 dB insertion loss requiring a gain of 3.8 V/V in the THS3095 to deliver 20 V_PP from the OPS output.
3. Figure 9-4 and Figure 9-5 show the frequency response and harmonic distortion performance of the dual output-voltage system. The frequency response is normalized to 0 dB to make bandwidth comparisons easier.