SBOS780C March   2016  – June 2021 THS3215

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: D2S
    6. 6.6  Electrical Characteristics: OPS
    7. 6.7  Electrical Characteristics: D2S + OPS
    8. 6.8  Electrical Characteristics: Midscale (DC) Reference Buffer
    9. 6.9  Typical Characteristics: D2S + OPS
    10. 6.10 Typical Characteristics: D2S Only
    11. 6.11 Typical Characteristics: OPS Only
    12. 6.12 Typical Characteristics: Midscale (DC) Reference Buffer
    13. 6.13 Typical Characteristics: Switching Performance
    14. 6.14 Typical Characteristics: Gain Drift
  7. Parameter Measurement Information
    1. 7.1 Overview
    2. 7.2 Frequency Response Measurement
    3. 7.3 Harmonic Distortion Measurement
    4. 7.4 Noise Measurement
    5. 7.5 Output Impedance Measurement
    6. 7.6 Step-Response Measurement
    7. 7.7 Feedthrough Measurement
    8. 7.8 Midscale Buffer ROUT Versus CLOAD Measurement
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Differential to Single-Ended Stage (D2S) With Fixed Gain of 2 V/V (Pins 2, 3, 6, and 14)
      2. 8.3.2 Midscale (DC) Reference Buffer (Pin 1 and Pin 15)
      3. 8.3.3 Output Power Stage (OPS) (Pins 4, 7, 9, 10, 11, and 12)
        1. 8.3.3.1 Output DC Offset and Drift for the OPS
        2. 8.3.3.2 OPS Harmonic Distortion (HD) Performance
        3. 8.3.3.3 Switch Feedthrough to the OPS
        4. 8.3.3.4 Driving Capacitive Loads
      4. 8.3.4 Digital Control Lines
    4. 8.4 Device Functional Modes
      1. 8.4.1 Full-Signal Path Mode
        1. 8.4.1.1 Internal Connection With Fixed Common-Mode Output Voltage
        2. 8.4.1.2 Internal Connection With Adjustable Common-Mode Output Voltage
        3. 8.4.1.3 External Connection
      2. 8.4.2 Dual-Output Mode
      3. 8.4.3 Differential I/O Voltage Mode
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Typical Applications
        1. 9.1.1.1 High-Frequency, High-Voltage, Dual-Output Line Driver for AWGs
          1. 9.1.1.1.1 Design Requirements
          2. 9.1.1.1.2 Detailed Design Procedure
          3. 9.1.1.1.3 Application Curves
        2. 9.1.1.2 High-Voltage Pulse-Generator
          1. 9.1.1.2.1 Design Requirements
          2. 9.1.1.2.2 Detailed Design Procedure
          3. 9.1.1.2.3 Application Curves
        3. 9.1.1.3 Single-Supply, AC-Coupled, Piezo Element Driver
          1. 9.1.1.3.1 Detailed Design Procedure
        4. 9.1.1.4 Output Common-Mode Control Using the Midscale Buffer as a Level Shifter
          1. 9.1.1.4.1 Detailed Design Procedure
        5. 9.1.1.5 Differential I/O Driver With independent Common-Mode Control
          1. 9.1.1.5.1 Detailed Design Procedure
  10. 10Power Supply Recommendations
    1. 10.1 Thermal Considerations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 TINA-TI (Free Software Download)
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Driving Capacitive Loads

The OPS can drive heavy capacitive loads very well, as shown in Figure 6-43 to Figure 6-48. All high-speed amplifiers benefit from the addition of an external series resistor to isolate the load capacitor from the feedback loop. Not using a series isolation resistor often leads to response peaking and possibly oscillation. If frequency response flatness under capacitive load is the design goal, use slightly higher RF values at the lower gains. Target a slightly-higher feedback transimpedance to increase the nominal phase margin before the capacitive load acts to decrease it. Using a higher RF value increases the frequency response flatness across a range of capacitive loads using lower external series resistor values. Although the suggested RF and RG values of Table 8-1 apply when driving a 100 Ω load, if the intended load is capacitive (for example, a passive filter with a shunt capacitor as the first element, another amplifier, or a Piezo element), use the values reported in Table 8-6 as a starting point. The values in Table 8-6 were used to generate Figure 6-43 and Figure 6-44. The results come from a nominal total feedback transimpedance target of 405 Ω (versus 351 Ω used for Table 8-3), and includes the internal 18.5 kΩ resistor in the design. Table 8-6 finds the least error to target gain in the selection of standard resistor values, and limits the minimum RG to 20 Ω. The gains calculated here put 18.5 kΩ in parallel with the reported external standard value RF.

Table 8-6 Suggested RF and RG Over Gain When Driving a Capacitive Load
TARGET GAIN
(V/V)
BEST RF
(Ω)
BEST RG (Ω) CALCULATED GAIN GAIN ERROR
(%)
(V/V) (dB)
1.5 487 953 1.494 3.488 –0..389
2 432 422 1.995 6 –0.233
2.5 402 261 2.501 7.963 0.048
3 332 162 3.006 9.559 0.191
3.5 274 107 3.515 10.917 0.416
4 221 73.2 3.974 11.984 –0.662
4.5 165 46.4 4.513 13.090 0.295
5 158 39.2 4.984 13.952 –0.320
5.5 165 36.5 5.467 14.755 –0.602
6 169 33.2 6.029 15.605 0.486
6.5 169 30.1 6.547 16.321 0.729
7 174 28.7 6.989 16.888 –0.161
7.5 174 26.7 7.437 17.429 –0.833
8 178 24.9 8.060 18.127 0.753
8.5 178 23.2 8.578 18.668 0.915
9 178 22.1 8.955 19.041 –0.499
9.5 182 21 9.558 19.608 0.613
10 187 20.5 10.006 20.005 0.056

As the capacitive load or amplifier gain increases, the series resistor values can be reduced to hold a flat response (see Figure 6-43). See Figure 6-44 for the measured SSBW shapes for various capacitive loads configured with the suggested series resistor from the output of the OPS and the RF and RG values suggested in Table 8-6 for a gain of 2.5 V/V. This measurement includes a 200 Ω shunt resistor in parallel with the capacitive load as a measurement path.

Figure 6-45 and Figure 6-46 demonstrate the OPS harmonic distortion performance when driving a range of capacitive loads. These figures show suitable performance for large-signal, piezo-driver applications. If voltage swings higher than 12 VPP are required, consider driving the OPS output into a step-up transformer. The high peak-output current for the OPS supports very fast charging edge rates into heavy capacitive loads, as shown in the step response plots (see Figure 6-47 and Figure 6-48). This peak current occurs near the center of the transition time driving a capacitive load. Therefore, the I × R drop to the capacitive load through the series resistor is at a maximum at midtransition, and 0 V at the extremes (low dV/dT points). For even better performance driving heavy capacitive loads, consider using the THS3217, a DAC output amplifier with higher output current and slew rate.