5.3.3.1 nPORRST Electrical and Timing Requirements
Table 5-4 Electrical Requirements for nPORRST
NO.
MIN
MAX
UNIT
VCCPORL
VCC low supply level when nPORRST must be active during power up
0.5
V
VCCPORH
VCC high supply level when nPORRST must remain active during power up and become active during power down
1.14
V
VCCIOPORL
VCCIO / VCCP low supply level when nPORRST must be active during power up
1.1
V
VCCIOPORH
VCCIO / VCCP high supply level when nPORRST must remain active during power up and become active during power down
3.0
V
VIL(PORRST)
Low-level input voltage of nPORRST VCCIO > 2.5V
0.2 * VCCIO
V
Low-level input voltage of nPORRST VCCIO < 2.5V
0.5
3
tsu(PORRST)
Setup time, nPORRST active before VCCIO and VCCP > VCCIOPORL during power up
0
ms
6
th(PORRST)
Hold time, nPORRST active after VCC > VCCPORH
1
ms
7
tsu(PORRST)
Setup time, nPORRST active before VCC < VCCPORH during power down
2
µs
8
th(PORRST)
Hold time, nPORRST active after VCCIO and VCCP > VCCIOPORH
1
ms
9
th(PORRST)
Hold time, nPORRST active after VCC < VCCPORL
0
ms
tf(nPORRST)
Filter time nPORRST terminal; pulses less than MIN will be filtered out, pulses greater than MAX will generate a reset. Pulses greater than MIN but less than MAX may or may not generate a reset.
475
2000
ns
A. Figure 5-1 shows that there is no timing dependency between the ramp of the VCCIO and the VCC supply voltages.