SCDS436 September   2023 TMUX9616

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Thermal Information
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Electrical Characteristics: TMUX9616
    6. 6.6 Switching Characteristics: TMUX9616
    7. 6.7 Digital Timings: TMUX9616
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Off-Leakage Current
    2. 7.2 Device Turn On/Off Time
    3. 7.3 Off Isolation
    4. 7.4 Inter-Channel Crosstalk
    5. 7.5 Output Voltage Spike
    6. 7.6 Switch DC Offset Voltage
    7. 7.7 Isolation Diode Current
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Wide Input Signal Range (up to ±110 V, 220 VPP)
      2. 8.3.2 Bidirectional Operation
      3. 8.3.3 Device Digital Logic Control
      4. 8.3.4 Latch-Up Immunity by Device Construction
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Mode
      2. 8.4.2 Device Power Up
    5. 8.5 Device Logic Table
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.3 Device Digital Logic Control

The TMUX9616 is controlled by a SPI interface to a 16-bit shift register, and a CLR pin. The SPI interface can run at speeds up to 72 MHz. It can also be run with 1.8 V – 5 V logic levels (set by logic supply VLL). The DIN pin will take in the data for the 16-bit register, and CLK will take in the clock signal. Data is shifted in on the DIN pin with the most-significant bit (MSB) first. After writing in 16 bits into the shift register using DIN and CLK, LE is then used to latch the state of the switches in the shift register to change the state of the switches in analog. The switches go to a state of retaining their present state on the rising edge of the LE pin. When LE is high, updates to the shift register does not change the condition of the 16 switches until LE is made low again. When LE is low, the shift register data flows through the latch and the condition of the 16 switches will be changed as the shift register is updated.

TMUX9616 16-bit shift register can be used in daisy chain mode. This is done by connecting the DOUT pin of the first TMUX9616 device to the DIN pin of the next TMUX9616 device in the chain. All TMUX9616 in the daisy chain will share the same source CLK signal (the CLK pin of each device in the daisy chain will be shorted together). DOUT is the data output pin of the 16th bit of the shift register, which is the data on DIN clock shifted by 16 clock cycles. The LE pin of each device in the chain will be shorted together, using the same LE source.

Assuming N number of TMUX9616 devices in the daisy chain, the standard method of writing to the shift registers is to write 16 * N bits of data, corresponding to each switch in the daisy chain, with LE set high. Once all 16 * N bits are written into the shift register, LE is pulsed low for at least tWLE to update the condition of the 16 * N switches in the daisy chain to the new state recorded in the shift register. Then LE is set high again so that the state of the switches will not change until the next 16 * N bits are written into the shift register (and LE is pulsed low again following the 16 * N bit write).

The CLR pin, when asserted high, causes all the 16 switches in TMUX9616 to turn OFF, regardless of the state of the bits in the 16-bit shift register. When the CLR pin asserted low, the switches will then use the shift register again to set its values.

For more details on programming the shift register and the logic state of each switch, see the Device Logic Table section. For more details of programming the shift register with the correct digital timings, see the Timing Diagrams section and the Digital Timings table. For more details on the maximum speeds obtainable in daisy chain mode depending on device configuration, see the Switching Characteristics table. Figure 8-1 shows more details on how to connect the TMUX9616 device's in daisy chain mode.

GUID-20230515-SS0I-JWMS-RKCD-JCJMXFC54P7R-low.svg Figure 8-1 Daisy Chain System Block Diagram