SLOS498B September   2006  – September 2015 TPA2006D1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Operating Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Fully Differential Amplifier
        1. 9.3.1.1 Advantages of Fully Differential Amplifiers
      2. 9.3.2 Efficiency and Thermal Information
      3. 9.3.3 Eliminating the Output Filter With the TPA2006D1 Device
        1. 9.3.3.1 Effect on Audio
        2. 9.3.3.2 Traditional Class-D Modulation Scheme
        3. 9.3.3.3 TPA2006D1 Device Modulation Scheme
        4. 9.3.3.4 Efficiency: Why A Filter is Needed With the Traditional Class-D Modulation Scheme
        5. 9.3.3.5 Effects of Applying a Square Wave into a Speaker
        6. 9.3.3.6 When to Use an Output Filter
      4. 9.3.4 Thermal and Short-Circuit Protection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Summing Input Signals with the TPA2006D1 Device
        1. 9.4.1.1 Summing Two Differential Input Signals
        2. 9.4.1.2 Summing a Differential Input Signal and a Single-Ended Input Signal
        3. 9.4.1.3 Summing Two Single-Ended Input Signals
      2. 9.4.2 Shutdown Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Component Selection
        2. 10.2.2.2 Input Resistors (RI)
        3. 10.2.2.3 Decoupling Capacitor (CS)
        4. 10.2.2.4 Input Capacitors (CI)
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
  11. 11Power Supply Recommendations
    1. 11.1 Power Supply Decoupling Capacitors
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Community Resources
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VDD Supply voltage In active mode –0.3 6 V
In SHUTDOWN mode –0.3 7 V
VI Input voltage –0.3 VDD + 0.3 Ω
RL Load resistance 2.5 ≤ VDD ≤ 4.2 V 3.2 Ω
4.2 < VDD ≤ 6 V 6.4
TA Operating free-air temperature –40 85 °C
TJ Operating junction temperature –40 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD Supply voltage 2.5 5.5 V
VIH High-level input voltage SHUTDOWN 1.3 VDD V
VIL Low-level input voltage SHUTDOWN 0 0.35 V
RI Input resistor Gain ≤ 20 V/V (26 dB) 15 kΩ
VIC Common mode input voltage range VDD = 2.5 V, 5.5 V, CMRR ≤ –49 dB 0.5 VDD–0.8 V
TA Operating free-air temperature –40 85 °C

7.4 Thermal Information

THERMAL METRIC(1) TPA2006D1 UNIT
VSON (DRB)
8 PINS
RθJA Junction-to-ambient thermal resistance 50.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 66.2 °C/W
RθJB Junction-to-board thermal resistance 25.9 °C/W
ψJT Junction-to-top characterization parameter 1.4 °C/W
ψJB Junction-to-board characterization parameter 26 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 7 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

TA = 25°C, over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
|VOS| Output offset voltage (measured differentially) VI = 0 V, AV = 2 V/V, VDD = 2.5 V to 5.5 V 25 mV
PSRR Power supply rejection ratio VDD = 2.5 V to 5.5 V –75 –55 dB
CMRR Common mode rejection ratio VDD = 2.5 V to 5.5 V, VIC = VDD/2 to 0.5 V,
VIC = VDD/2 to VDD –0.8 V		 –68 –49 dB
|IIH| High-level input current VDD = 5.5 V, VI = 5.8 V 100 μA
|IIL| Low-level input current VDD = 5.5 V, VI = –0.3 V 5 μA
I(Q) Quiescent current VDD = 5.5 V, no load 3.4 4.9 mA
VDD = 3.6 V, no load 2.8
VDD = 2.5 V, no load 2.2 3.2
I(SD) Shutdown current V(SHUTDOWN)= 0.35 V, VDD = 2.5 V to 5.5 V 0.5 2 μA
rDS(on) Static drain-source on-state
resistance		 VDD = 2.5 V 770 mΩ
VDD = 3.6 V 590
VDD = 5.5 V 500
Output impedance in SHUTDOWN V(SHUTDOWN) = 0.35 V >1 kΩ
f(sw) Switching frequency VDD = 2.5 V to 5.5 V 200 250 300 kHz
Gain VDD = 2.5 V to 5.5 V
TPA2006D1 eq_min_los417.gif
TPA2006D1 eq_typ_los417.gif
TPA2006D1 eq_max_los417.gif
TPA2006D1 eq_unit_los417.gif
Resistance from shutdown to GND 300 kΩ

7.6 Operating Characteristics

TA = 25°C, Gain = 2 V/V, RL = 8 Ω (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PO Output power THD + N = 10%, f = 1 kHz, RL = 8 Ω VDD = 5 V 1.45 W
VDD = 3.6 V 0.73
VDD = 2.5 V 0.33
THD + N = 1%, f = 1 kHz, RL = 8 Ω VDD = 5 V 1.19 W
VDD = 3.6 V 0.59
VDD = 2.5 V 0.26
THD+N Total harmonic distortion plus
noise		 VDD = 5 V, PO = 1 W, RL = 8 Ω, f = 1 kHz 0.19%
VDD = 3.6 V, PO = 0.5 W, RL = 8 Ω, f = 1 kHz 0.19%
VDD = 2.5 V, PO = 200 mW, RL = 8 Ω, f = 1 kHz 0.20%
kSVR Supply ripple rejection ratio VDD = 3.6 V, Inputs ac-grounded
with Ci = 2 μF		 f = 217 Hz,
V(RIPPLE) = 200 mVPP 		–67 dB
SNR Signal-to-noise ratio VDD = 5 V, PO = 1 W, RL = 8 Ω, A-weighted 97 dB
Vn Output voltage noise VDD = 3.6 V, f = 20 Hz to 20 kHz,
Inputs ac-grounded with Ci = 2 μF		 No weighting 48 μVRMS
A weighting 36
CMRR Common mode rejection ratio VDD = 3.6 V, VIC = 1 VPP f = 217 Hz –63 dB
ZI Input impedance 142 150 158 kΩ
Start-up time from shutdown VDD = 3.6 V 1 ms

7.7 Typical Characteristics

TPA2006D1 tc_eff_los498.gif
Figure 1. Efficiency vs Output Power
TPA2006D1 tc_pow1_los498.gif
Figure 3. Power Dissipation vs Output Power
TPA2006D1 eff_po_los498.gif
Figure 2. Efficiency vs Output Power
TPA2006D1 tc_sup1_los498.gif
Figure 4. Supply Current vs Output Power
TPA2006D1 tc_qcurr_los498.gif
Figure 5. Quiescent Current vs Supply Voltage
TPA2006D1 po_rl_los498.gif
Figure 7. Output Power vs Load Resistance
TPA2006D1 tc_out2_los498.gif
Figure 9. Output Power vs Supply Voltage
TPA2006D1 thd_po_8ohm_los498.gif
Figure 11. Total Harmonic Distortion + Noise vs Output Power
TPA2006D1 thd_frq_5v_los498.gif
Figure 13. Total Harmonic Distortion + Noise vs Frequency
TPA2006D1 thd_frq_25v_los498.gif
Figure 15. Total Harmonic Distortion + Noise vs Frequency
TPA2006D1 thdn2_f_los498.gif
Figure 17. Total Harmonic Distortion + Noise vs Frequency
TPA2006D1 tc_total6_los417.gif
Figure 19. Total Harmonic Distortion + Noise vs Common Mode Input Voltage
TPA2006D1 tc_supr2_los498.gif
Figure 21. Supply Ripple Rejection Ratio vs Frequency
TPA2006D1 tc_gsm1_los417.gif
Figure 23. GSM Power Supply Rejection vs Frequency
TPA2006D1 tc_com_los417.gif
Figure 25. Common-mode Rejection Ratio vs Frequency
TPA2006D1 tc_shut_los417.gif
Figure 6. Supply Current vs Shutdown Voltage
TPA2006D1 po2_rl_los498.gif
Figure 8. Output Power vs Load Resistance
TPA2006D1 po_vdd_los498.gif
Figure 10. Output Power vs Supply Voltage
TPA2006D1 thdn_po_los498.gif
Figure 12. Total Harmonic Distortion + Noise vs Output Power
TPA2006D1 thd_frq_36v_los498.gif
Figure 14. Total Harmonic Distortion + Noise vs Frequency
TPA2006D1 thdn_f_los498.gif
Figure 16. Total Harmonic Distortion + Noise vs Frequency
TPA2006D1 thdn3_f_los498.gif
Figure 18. Total Harmonic Distortion + Noise vs Frequency
TPA2006D1 tc_supr_los498.gif
Figure 20. Supply Ripple Rejection Ratio vs Frequency
TPA2006D1 tc_gsm_los417.gif
Figure 22. GSM Power Supply Rejection vs Time
TPA2006D1 tc_supr3_los417.gif
Figure 24. Supply Ripple Rejection Ratio vs
DC Common Mode Voltage
TPA2006D1 tc_com1_los417.gif
Figure 26. Common-mode Rejection Ratio vs
Common-mode Input Voltage