SLUSD62 December   2017 TPS40345

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Voltage Reference
      2. 7.3.2 Enable Functionality, Start-Up Sequence and Timing
      3. 7.3.3 Soft-Start Time
      4. 7.3.4 Oscillator and Frequency Spread Spectrum (FSS)
      5. 7.3.5 Overcurrent Protection
      6. 7.3.6 Drivers
      7. 7.3.7 Prebias Start-Up
      8. 7.3.8 Power Good
      9. 7.3.9 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
        1. 7.4.1.1 UVLO
        2. 7.4.1.2 Disable
        3. 7.4.1.3 Calibration
        4. 7.4.1.4 Converting
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Selecting the Switching Frequency
        2. 8.2.2.2  Inductor Selection (L1)
        3. 8.2.2.3  Output Capacitor Selection (C12)
        4. 8.2.2.4  Peak Current Rating of Inductor
        5. 8.2.2.5  Input Capacitor Selection (C8)
        6. 8.2.2.6  MOSFET Switch Selection (Q1 and Q2)
        7. 8.2.2.7  Bootstrap Capacitor (C6)
        8. 8.2.2.8  VDD Bypass Capacitor (C7)
        9. 8.2.2.9  BP Bypass Capacitor (C5)
        10. 8.2.2.10 Short-Circuit Protection (R11)
        11. 8.2.2.11 Feedback Divider (R4, R5)
        12. 8.2.2.12 Compensation: (C2, C3, C4, R3, R6)
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS40345 a cost-optimized synchronous buck controllers providing high-end features to construct high-performance DC-DC converters. Prebias capability eliminates concerns about damaging sensitive loads during start-up. Programmable overcurrent protection levels and hiccup overcurrent fault recovery maximize design flexibility and minimize power dissipation in the event of a prolonged output short. frequency spread spectrum (FSS) feature reduces peak EMI noise by spreading the initial energy of each harmonic along a frequency band, thus giving a wider spectrum with lower amplitudes.

8.2 Typical Applications

For this 20-A, 12-V to 1.2-V design, the 600-kHz TPS40345 was selected for a balance between small size and high efficiency.

TPS40345 de04_schem_lus964.gif Figure 12. TPS40345 Design Example Schematic

8.2.1 Design Requirements

For this example, follow the design parameters listed in Table 1.

Table 1. Design Example Electrical Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage 8 14 V
VINripple Input ripple IOUT = 20 A 0.5 V
VOUT Output voltage 0 A ≤ IOUT ≤ 20 A 1.164 1.2 1.236 V
Line regulation 8 V ≤ VIN ≤ 14 V 0.5%
Load regulation 0 A ≤ IOUT ≤ 20 A 0.5%
VRIPPLE Output ripple IOUT = 20 A 36 mV
VOVER Output overshoot 5 A ≤ IOUT ≤ 15 A 100 mV
VUNDER Output undershoot 5 A ≤ IOUT ≤ 15 A 100 mV
IOUT Output current 8 V ≤ VIN ≤ 14 V 0 20 A
tSS Soft-start time VIN = 12 V 1.5 ms
ISCP Short-circuit current trip point 26 A
fSW Switching frequency 600 kHz
Size 1.5 in2

8.2.2 Detailed Design Procedure

8.2.2.1 Selecting the Switching Frequency

To achieve the small size for this design the TPS40345, with fSW = 600 kHz, is selected for minimal external component size.

8.2.2.2 Inductor Selection (L1)

Synchronous buck power inductors are typically sized for approximately 30% peak-to-peak ripple current (IRIPPLE).

Given this target ripple current, the required inductor size can be calculated in Equation 3.

Equation 3. TPS40345 4equation1.gif

Selecting a standard 300-nH inductor value, solve for IRIPPLE = 6 A

The RMS current through the inductor is approximated by Equation 4.

Equation 4. TPS40345 4equation2.gif

8.2.2.3 Output Capacitor Selection (C12)

The selection of the output capacitor is typically driven by the output transient response. Equation 5 and Equation 6 overestimate the voltage deviation to account for delays in the loop bandwidth and can be used to determine the required output capacitance.

Equation 5. TPS40345 deq_vover_lus964.gif
Equation 6. TPS40345 deq_vunderx_lus964.gif

If VIN(min) > 2 × VOUT, use overshoot (Equation 5) to calculate minimum output capacitance. If VIN(min) < 2 × VOUT, use undershoot (Equation 6) to calculate minimum output capacitance.

Equation 7. TPS40345 4equation3.gif

With a minimum capacitance, the maximum allowable ESR is determined by the maximum ripple voltage and is approximated by Equation 8.

Equation 8. TPS40345 4equation4.gif

Two 47-µF and one 220-µF capacitors are selected to provide more than 250 µF of minimum capacitance and 5.2 mΩ of ESR.

8.2.2.4 Peak Current Rating of Inductor

With output capacitance, it is possible to calculate the charge current during start-up and determine the minimum saturation current rating for the inductor. The start-up charging current is approximated by Equation 9.

Equation 9. TPS40345 4equation5.gif
Equation 10. TPS40345 4equation6.gif

Table 2. Inductor Requirements

PARAMETER VALUE UNIT
L Inductance 300 nH
IL(rms) RMS current (thermal rating) 20.07 A
IL(peak) Peak current (saturation rating) 23.25 A

8.2.2.5 Input Capacitor Selection (C8)

The input voltage ripple is divided between capacitance and ESR. For this design VRIPPLE(cap) = 150 mV and VRIPPLE(esr) = 150 mV. The minimum capacitance and maximum ESR are estimated by Equation 11.

Equation 11. TPS40345 4equation7.gif
Equation 12. TPS40345 4equation8.gif

The RMS current in the input capacitors is estimated by Equation 13.

Equation 13. TPS40345 4equation9.gif

Three 1210, 10-µF, 25-V, X5R ceramic capacitors are selected. Higher voltage capacitors are selected to minimize capacitance loss at the DC bias voltage to ensure the capacitors allow sufficient capacitance at the working voltage.

8.2.2.6 MOSFET Switch Selection (Q1 and Q2)

Reviewing available TI NexFET MOSFETs using the TI NexFET MOSFET selection tool, the CSD16410Q5A and CSD16321Q5 5-mm × 6-mm MOSFETs are selected.

These two FETs have maximum total gate charges of 5 nC and 10 nC, respectively.

8.2.2.7 Bootstrap Capacitor (C6)

To ensure proper charging of the high-side FET gate, limit the ripple voltage on the boost capacitor to less than 50 mV.

Equation 14. TPS40345 4equation10.gif

8.2.2.8 VDD Bypass Capacitor (C7)

Per this TPS40345 data sheet, select a 1-uF X5R or better ceramic bypass capacitor for VDD.

8.2.2.9 BP Bypass Capacitor (C5)

Per the TPS40345 data sheet, a minimum 1-uF ceramic capacitance is required to stabilize the BP regulator. To limit regulator noise to less than 10 mV, the value of the bypass capacitor is calculated in Equation 15.

Equation 15. TPS40345 4equation11.gif

Because Q2 is larger than Q1, and the total gate charge of Q2 is 10 nC, a BP capacitor of 1 µF is calculated. A standard value of 1 µF is selected to limit noise on the BP regulator.

8.2.2.10 Short-Circuit Protection (R11)

The TPS40345 uses the negative drop across the low-side FET at the end of the OFF-time to measure the inductor current. Allowing for 30% over maximum load and 20% rise in RDS(on)Q1 for self-heating, the voltage drop across the low-side FET at current limit is given by Equation 16.

Equation 16. TPS40345 4equation12.gif

The TPS40345 internal temperature coefficient helps compensate for the MOSFET’s RDS(on) temperature coefficient, so the current limit programming resistor is selected by Equation 17.

Equation 17. TPS40345 4equation13.gif

8.2.2.11 Feedback Divider (R4, R5)

The TPS40345 controller uses a full operational amplifier with an internally fixed 0.6-V reference. R4 is selected between 10 kΩ and 50 kΩ for a balance of feedback current and noise immunity. With R4 set to 10 kΩ, The output voltage is programmed with a resistor divider given by Equation 18.

Equation 18. TPS40345 4equation14.gif

8.2.2.12 Compensation: (C2, C3, C4, R3, R6)

Using the TPS40k Loop Stability Tool for 100-kHz bandwidth and 60° phase margin with a R4 value of 10.0 kΩ, the following values are returned.

  • C4 = 680 pF
  • C5 = 100 pF
  • C6 = 680 pF
  • R1 = 10 kΩ
  • R2 = 1.5 kΩ

8.2.3 Application Curves

TPS40345 de04eff_v_iload_lus964.gif
Figure 13. Efficiency vs Load Current
TPS40345 de04_ripple_lus964.png Figure 15. Output Ripple 10 mV/div, 2-µs/div, 20-MHz Bandwidth
TPS40345 de04gainphase_v_f_lus964.gif Figure 14. Gain and Phase vs Frequency