SLUSD62 December   2017 TPS40345

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Voltage Reference
      2. 7.3.2 Enable Functionality, Start-Up Sequence and Timing
      3. 7.3.3 Soft-Start Time
      4. 7.3.4 Oscillator and Frequency Spread Spectrum (FSS)
      5. 7.3.5 Overcurrent Protection
      6. 7.3.6 Drivers
      7. 7.3.7 Prebias Start-Up
      8. 7.3.8 Power Good
      9. 7.3.9 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
        1. 7.4.1.1 UVLO
        2. 7.4.1.2 Disable
        3. 7.4.1.3 Calibration
        4. 7.4.1.4 Converting
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Selecting the Switching Frequency
        2. 8.2.2.2  Inductor Selection (L1)
        3. 8.2.2.3  Output Capacitor Selection (C12)
        4. 8.2.2.4  Peak Current Rating of Inductor
        5. 8.2.2.5  Input Capacitor Selection (C8)
        6. 8.2.2.6  MOSFET Switch Selection (Q1 and Q2)
        7. 8.2.2.7  Bootstrap Capacitor (C6)
        8. 8.2.2.8  VDD Bypass Capacitor (C7)
        9. 8.2.2.9  BP Bypass Capacitor (C5)
        10. 8.2.2.10 Short-Circuit Protection (R11)
        11. 8.2.2.11 Feedback Divider (R4, R5)
        12. 8.2.2.12 Compensation: (C2, C3, C4, R3, R6)
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

  • For MOSFET or power block layout, follow the layout recommendations provided for the MOSFET or power block selected.
  • Connect VDD to VIN as close as possible to the drain connection of the high-side FET to avoid introducing additional drop, which could trigger short-circuit protection.
  • Place VDD and BP to GND capacitors within 2 mm of the device and connected to the thermal pad (GND).
  • Connect the FB to GND resistor to the thermal tab (GND) with a minimum 10-mil wide trace.
  • Place VOUT to FB resistor within 2 mm of the FB pin.
  • Connect the EN/SS-to-GND capacitor to the thermal tab (GND) with a minimum 10-mil-wide trace. It may share this trace with FB to GND.
  • If a BJT or MOSFET is used to disable EN/SS, place it within 5 mm of the device.
  • If a COMP to GND resistor is used, place it within 5 mm of the device.
  • All COMP and FB traces should be kept minimum line width and as short as possible to minimize noise coupling.
  • EN/SS should not be routed more than 20 mm from the device.
  • If multiple layers are used, extend GND under all components connected to FB, COMP and EN/SS to reduce noise sensitivity.
  • HDRV and LDRV must provide short, low inductance paths of 5 mm or less to the gates of the MOSFETs or power block.
  • Place no more than 1 Ω of resistance between HDRV or LDRV and their MOSFET or power block gate pins.
  • LDRV / OC to GND current limit programming resistor may be placed on the far side of the MOSFET if necessary to ensure a short connection from LDRV to the gate of the low-side MOSFET.
  • Place the BOOT to SW resistor and capacitor within 4 mm of the device using a minimum of 10-mil-wide trace. The full width of the component pads are preferred for trace widths if design rules allow.
  • If via must be used between the HDRV, SW and LDRV pins and their respective MOSFET or power block connections, use a minimum of two vias to reduce parasitic inductance
  • Refer to the land pattern data for the preferred layout of thermal vias within the thermal pad.
  • TI recommends extending the top-layer copper area of the thermal pad (GND) beyond the package a minimum 3 mm between pins 1 and 10 and 5 and 6 to improve thermal resistance to ambient of the device.

10.2 Layout Example

TPS40345 top_cop_lus964.gif Figure 16. Top Copper With Components
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TPS40345 bot_int_lus964.gif Figure 18. Bottom Internal Copper Layout
TPS40345 top_int_lus964.gif Figure 17. Top Internal Copper Layout
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TPS40345 bot_cop_lus964.gif Figure 19. Bottom Copper Layer