SLUSDL4 February   2020 TPS59632-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings (1)
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  PWM Operation
      2. 7.3.2  Current Sensing
      3. 7.3.3  Load-line (Droop)
      4. 7.3.4  Load Transients
      5. 7.3.5  Overshoot Reduction (OSR)
      6. 7.3.6  Undershoot Reduction (USR)
      7. 7.3.7  Autobalance Current Sharing
      8. 7.3.8  PWM And SKIP Signals
      9. 7.3.9  Bias Power (V5A, VDD, And VINTF) UVLO
      10. 7.3.10 Start-Up Sequence
      11. 7.3.11 Power Good Operation
      12. 7.3.12 Analog Current Monitor, IMON, And Corresponding Digital Output Current
      13. 7.3.13 Fault Behavior
      14. 7.3.14 Output Under Voltage Protection (UVP)
      15. 7.3.15 Output Over Voltage Protection (OVP)
      16. 7.3.16 Over Current Protection (OCP)
      17. 7.3.17 Over Current Warning
      18. 7.3.18 Input Voltage Limits
      19. 7.3.19 VID Table
    4. 7.4 User Selections
    5. 7.5 I2C Interface Operation
      1. 7.5.1 Key For Protocol Examples
      2. 7.5.2 Protocol Examples
    6. 7.6 I2C Register Maps
      1. 7.6.1 Voltage Select Register (VSR) (Address = 00h)
      2. 7.6.2 IMON Register (Address = 03h)
      3. 7.6.3 VMAX Register (Address = 04h)
      4. 7.6.4 Power State Register (Address = 06h)
      5. 7.6.5 Slew Register (Address = 07h)
      6. 7.6.6 Lot Code Registers (Address = 10-13h)
      7. 7.6.7 Fault Register (Address = 14h)
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 3-Phase D-CAP+™, Step-Down Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Step 1: Select Switching Frequency
          2. 8.2.1.2.2  Step 2: Set The Slew Rate
          3. 8.2.1.2.3  Step 3: Set The I2C Address
          4. 8.2.1.2.4  Step 4: Determine Inductor Value And Choose Inductor
          5. 8.2.1.2.5  Step 5: Current Sensing Resistance
          6. 8.2.1.2.6  Step 6: Select Over Current Protection (OCP) Setting
          7. 8.2.1.2.7  Step 7: Current Monitor (IMON) Setting
          8. 8.2.1.2.8  Step 8: Set the Load-Line Slope
          9. 8.2.1.2.9  Step 9: Voltage Feedback Resistor Calculation
          10. 8.2.1.2.10 Step 10: Ramp Compensation Selection
          11. 8.2.1.2.11 Step 11 Overshoot Reduction (OSR) selection
          12. 8.2.1.2.12 Step 12: Undershoot Reduction (USR) selection
          13. 8.2.1.2.13 Step 13: Loop Compensation
        3. 8.2.1.3 Application Performance Plots
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1  Layout Guidelines
    2. 10.2  Layout Example
    3. 10.3  Current Sensing Lines
    4. 10.4  Feedback Voltage Sensing Lines
    5. 10.5  PWM And SKIP Lines
    6. 10.6  Power Chain Symmetry
    7. 10.7  Component Location
    8. 10.8  Grounding Recommendations
    9. 10.9  Decoupling Recommendations
    10. 10.10 Conductor Widths
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Over recommended temperature range, 4.5 V ≤ VV5A ≤ 5.5 V, 3.0 V ≤ VVDD ≤ 3.6 V, VGFB = GND, VVFB = VOUT, 0.7 < VFREQ-P ≤ VVREF (unless otherwise noted).
PARAMETER CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY: CURRENTS, UVLO AND POWER-ON-RESET
IV5-3P V5A supply current, 3-phase VVDAC < VVFB < (VVDAC + 100 mV), EN = ‘HI’ 3.6 6.0 mA
IVDD-3P VDD supply current, 3-phase VVDAC < VVFB < (VVDAC + 100 mV) , EN = ‘HI’; digital buses idle 0.2 0.8
IV5-1P V5A supply current, 1-phase VDAC < VFB < (VVDAC + 100 mV) EN = ‘HI’ 3.5 6.0
IVDD-1P VDD supply current, 1-phase VDAC < VFB < (VVDAC + 100 mV), EN = ‘HI’; digital buses idle 0.2 0.8
IV5STBY V5A standby current EN = ‘LO’ 125 200 µA
IVDDSTBY VDD standby current EN = ‘LO’ 23 40
IVINTF VINTF supply current All conditions; digital buses idle 1.7 5.0
VUVLOH V5A UVLO ‘OK’ threshold VVFB < 200 mV. Ramp up; VVDD > 3 V; EN = ’HI’; Switching begins. 4.2 4.4 4.52 V
VUVLOL V5A UVLO fault threshold Ramp down; EN = ’HI’; VVDD > 3 V; VVFB = 100 mV. Switching stops 4.00 4.2 4.35
V5POR V5A fault latch reset threshold Ramp down. EN = ‘HI’; VVDD > 3 V. Can restart if V5A rises to VUVLOH, and no other faults present. 1.2 1.9 2.5
V3UVLOH VDD UVLO ‘OK’ threshold VVFB < 200 mV. Ramp up; VV5A > 4.5 V; EN = ’HI’; Switching begins. 2.5 2.8 3.0
V3UVLOL Fault threshold Ramp down; EN = ’HI’; V5A > 4.5 V; VFB = 100 mV. Switching stops. 2.4 2.6 2.8
V3POR VDD fault latch Ramp down. EN = ‘HI’; V5A > 4.5 V. Can restart if VDD goes up to V3UVLOH, and no other faults present. 1.2 1.9 2.5
VINTFUVLOH VINTF UVLO OK Ramp up; EN = ’HI’; V5A > 4.5 V; VFB = 100 mV. 1.4 1.5 1.6
VINTFUVLOL VINTF UVLO falling Ramp down; EN = ’HI’; V5A > 4.5 V; VFB = 100 mV. 1.3 1.4 1.5
REFERENCES: VDAC, VREF, BOOT Voltage
VVIDSTP VID step size Change VID0 HI to LO to HI 10 mV
VDAC1 VFB tolerance 1.36 V ≤ VVFB ≤ 1.52 V, IOUT = 0 A –9 9
VDAC2 1.0 V ≤ VVFB ≤ 1.35 V; IOUT = 0 A –8 8
VDAC3 0.5 V ≤ VVFB ≤ 0.99 V; IOUT = 0 A –7 7
VVREF VREF output VREF output 4.5 V ≤ VV5A ≤ 5.5 V, IVREF = 0 A 1.66 1.700 1.74 V
VVREFSRC VREF output source 0 A ≤ IREF ≤ 500 µA, HP-2 –4 –3 mV
VVREFSNK VREF output sink –500 A ≤ IREF ≤ 0 A, HP-2 3 4
VVBOOT Internal VFB initial boot voltage Initial DAC boot voltage 0.8 V
DIFFERENTIAL VOLTAGE SENSE: VFB AND GFB
RVFB VFB/GFB Input resistance Not in fault, disable, or UVLO, VVFB = VDAC = 1.5 V
VGFB = 0 V, measure from VFB to GFB		 50 MΩ
VDELGND GFB Differential GND to GFB ±100 mV
ERROR AMPLIFIER, CURRENT AMPLIFIER, CURRENT SHARE
AV-EA Error amplifier total voltage gain(1) VFB to DROOP 80 dB
IEA_SR Error amplifier source current IDROOP, VVFB = VDAC + 50 mV, RCOMP = 1 kΩ 1 mA
IEA_SK Error amplifier sink current IDROOP, VVFB = VDAC –50 mV, RCOMP = 1 kΩ –1
ICS CS pin input bias current CSPx and CSNx –500 0.2 500 nA
ACSINT Internal current sense gain Gain from CSPx – CSNx to PWM comparator, RSKIP = Open 5.8 6.0 6.2 V/V
IBAL_TOL Internal current share tolerance VDAC = 1.70 V, VCSP1 – VCSN1 = VCSP2 – VCSN2 = VCSP3 – VCSN3 = VOCPP_MIN –3% +3%
RAMP SETTINGS
VRAMP Compensation ramp amplitude RRAMP = 20 kΩ +/- 1% 20 mV
RRAMP = 30 kΩ +/- 1% 60
RRAMP = 39 kΩ +/- 1% 100
RRAMP ≥ 150 kΩ +/- 1% 40
SLEW SETTINGS
SLSET Slew rate setting for VID change RSLEW = 20 kΩ +/- 1% 6 10 mV/µs
RSLEW = 24 kΩ +/- 1% 12 20
RSLEW = 30 kΩ +/- 1% 18 30
RSLEW = 39 kΩ +/- 1% 24 40
SLSTART Slew rate setting for start-up(1) EN goes high, RSLEW = 20 kΩ 3 5 mV/µs
ADDRESS SETTINGS
ADDR Address setting 3 LSB of I2C Address (ADDR = 100 0xxx) VSLEWA ≤ 0.25 V 000b
0.35 V ≤ VSLEWA ≤ 0.45 V 001b
0.55 V ≤ VSLEWA ≤ 0.65 V 010b
0.75 V ≤ VSLEWA ≤ 0.85 V 011b
0.95 V ≤ VSLEWA ≤ 1.05 V 100b
1.15 V ≤ VSLEWA ≤ 1.25 V 101b
1.35 V ≤ VSLEWA ≤ 1.45 V 110b
1.55 V ≤ VSLEWA ≤ VVREF 111b
OVERSHOOT REDUCTION (OSR) SETTINGS
VOSR Overshoot Reduction (OSR) Voltage set (1) RO-USR = 20 kΩ +/- 1% 100 mV
RO-USR = 24 kΩ +/- 1% 150
RO-USR = 30 kΩ +/- 1% 200
RO-USR = 39 kΩ +/- 1% 250
RO-USR = 56 kΩ +/- 1% 300
RO-USR = 75 kΩ +/- 1% 400
RO-USR = 100 kΩ +/- 1% 500
RO-USR = 150 kΩ +/- 1% OFF
UNDERSHOOT REDUCTION (USR) SETTINGS
VUSR Undershoot Reduction (USR) Voltage set (1) VO-USR < 0.25 V 40 mV
0.35 < VO-USR < 0.45 V 60
0.55 < VO-USR < 0.65 V 80
0.75 < VO-USR < 0.85 V 120
0.95 < VO-USR < 1.05 V 160
1.15 < VO-USR < 1.25 V 200
1.35 < VO-USR < 1.45 V 240
1.55 < VO-USR < VVREF OFF
OVER CURRENT PROTECTION (OCP) SETTINGS
VOCP OCP voltage (valley current limit at CSPx – CSNx) ROCP-I = 20 kΩ +/- 1% 5.0 7.0 9.0 mV
ROCP-I = 24 kΩ +/- 1% 7.0 10.0 13.0
ROCP-I = 30 kΩ +/- 1% 10.0 14.0 18.0
ROCP-I = 39 kΩ +/- 1% 15.0 19.0 23.0
ROCP-I = 56 kΩ +/- 1% 21.0 25.0 29.0
ROCP-I = 75 kΩ +/- 1% 28.0 32.0 36.0
ROCP-I = 100 kΩ +/- 1% 36.0 40.0 44.0
ROCP-I = 150 kΩ +/- 1% 45.0 49.0 53.0
CURRENT MONITOR (IMON)
VALADC IMON ADC output ∑∆CS = 0 mV, AIMON = 3.867 00h 00h 03h
∑∆CS = 4.5 mV, AIMON = 3.867 12h 19h 20h
∑∆CS = 22 mV, AIMON = 3.867 79h 80h 87h
∑∆CS = 44 mV, AIMON = 3.867 FAh FFh FFh
LRIMON IMON linear range Each phase, CSPx – CSNx 50 mV
PROTECTION: OVP, UVP, PGOOD
VOVPH Fixed OVP voltage VCSN1 > VOVPH for 1 µs 1.60 1.70 1.80 V
RSFTSTP Soft-stop transistor resistance Connected to CSN1 100 200 Ω
VPGDH PGOOD high threshold Measured at the VFB pin with respect to VID code, device latches OFF 185 245 mV
VPGDL PGOOD low threshold Measured at the VFB pin with respect to VID code, device latches OFF –348 –280
PWM ANDSKIP OUTPUTS: I/O VOLTAGE AND CURRENT
VP-S_L PWMx / SKIP – Low ILOAD = ± 1 mA 0.15 0.3 V
VP-S_H PWMx / SKIP – High ILOAD = ± 1 mA 4.2
VPW-SKLK PWMx / SKIP 3-state ILOAD = ± 100 µA 1.6 1.7 1.8
LOGIC INTERFACE: VOLTAGE AND CURRENT
RVRTTL Pulldown resistance SDA, V = 0.31 V 4 15 Ω
RVRPG PGOOD, V = 0.31 V 36 50
IVRTTLK Logic leakage current SDA, SCL = 1.8 V, PGOOD = 3.3 V –2 0.2 2 µA
VIL,I2C Low-level input voltage SCL, SDA, VINTF = 1.8 V 0.6 V
VIH,I2C High-level input voltage 1.2
VIL,EN EN Low-level input voltage 0.5 V
VIH,EN EN High-level input voltage 1.3
IENH I/O leakage, EN Leakage current , VEN = 1.8 V 24 40 µA
VBAT INPUT RESISTANCE
RVBAT VBAT resistance EN = HI 550 kΩ
EN = LOW 50 MΩ
(1) Specified by design. Not production tested.