SWCS138E June   2017  – December 2022 TPS650864

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: Total Current Consumption
    6. 7.6  Electrical Characteristics: Reference and Monitoring System
    7. 7.7  Electrical Characteristics: Buck Controllers
    8. 7.8  Electrical Characteristics: Synchronous Buck Converters
    9. 7.9  Electrical Characteristics: LDOs
    10. 7.10 Electrical Characteristics: Load Switches
    11. 7.11 Digital Signals: I2C Interface
    12. 7.12 Digital Input Signals (CTLx)
    13. 7.13 Digital Output Signals (IRQB, GPOx)
    14. 7.14 Timing Requirements
    15. 7.15 Switching Characteristics
    16. 7.16 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1  Overview
    2. 8.2  Functional Block Diagram
    3. 8.3  TPS6508640 Design and Settings
      1. 8.3.1 TPS6508640 OTP Summary
    4. 8.4  TPS65086401 Design and Settings
      1. 8.4.1 TPS65086401 OTP Summary
      2.      31
    5. 8.5  TPS6508641 Design and Settings
      1. 8.5.1 TPS6508641 OTP Summary
    6. 8.6  TPS65086470 Design and Settings
      1. 8.6.1 TPS65086470 OTP Summary
    7. 8.7  SMPS Voltage Regulators
      1. 8.7.1 Controller Overview
      2. 8.7.2 Converter Overview
      3. 8.7.3 DVS
      4. 8.7.4 Decay
      5. 8.7.5 Current Limit
    8. 8.8  LDOs and Load Switches
      1. 8.8.1 VTT LDO
      2. 8.8.2 LDOA1–LDOA3
      3. 8.8.3 Load Switches
    9. 8.9  Power Goods (PGOOD or PG) and GPOs
    10. 8.10 Power Sequencing and VR Control
      1. 8.10.1 CTLx Sequencing
      2. 8.10.2 PG Sequencing
      3. 8.10.3 Enable Delay
      4. 8.10.4 Power-Up Sequence
      5. 8.10.5 Power-Down Sequence
      6. 8.10.6 Sleep State Entry and Exit
      7. 8.10.7 Emergency Shutdown
    11. 8.11 Device Functional Modes
      1. 8.11.1 Off Mode
      2. 8.11.2 Standby Mode
      3. 8.11.3 Active Mode
    12. 8.12 I2C Interface
      1. 8.12.1 F/S-Mode Protocol
    13. 8.13 Register Maps
      1. 8.13.1  Register Map Summary
      2. 8.13.2  DEVICEID1: 1st PMIC Device and Revision ID Register (offset = 00h) [reset = X]
      3. 8.13.3  DEVICEID2: 2nd PMIC Device and Revision ID Register (offset = 01h) [reset = X]
      4. 8.13.4  IRQ: PMIC Interrupt Register (offset = 02h) [reset = 0000 0000]
      5. 8.13.5  IRQ_MASK: PMIC Interrupt Mask Register (offset = 03h) [reset = 1111 1111]
      6. 8.13.6  PMICSTAT: PMIC Status Register (offset = 04h) [reset = 0000 0000]
      7. 8.13.7  SHUTDNSRC: PMIC Shut-Down Event Register (offset = 05h) [reset = 0000 0000]
      8. 8.13.8  BUCK1CTRL: BUCK1 Control Register (offset = 20h) [reset = X]
      9. 8.13.9  BUCK2CTRL: BUCK2 Control Register (offset = 21h) [reset = X]
      10. 8.13.10 BUCK3DECAY: BUCK3 Decay Control Register (offset = 22h) [reset = X]
      11. 8.13.11 BUCK3VID: BUCK3 VID Register (offset = 23h) [reset = X]
      12. 8.13.12 BUCK3SLPCTRL: BUCK3 Sleep Control VID Register (offset = 24h) [reset = X]
      13. 8.13.13 BUCK4CTRL: BUCK4 Control Register (offset = 25h) [reset = X]
      14. 8.13.14 BUCK5CTRL: BUCK5 Control Register (offset = 26h) [reset = X]
      15. 8.13.15 BUCK6CTRL: BUCK6 Control Register (offset = 27h) [reset = X]
      16. 8.13.16 LDOA2CTRL: LDOA2 Control Register (offset = 28h) [reset = X]
      17. 8.13.17 LDOA3CTRL: LDOA3 Control Register (offset = 29h) [reset = X]
      18. 8.13.18 DISCHCTRL1: 1st Discharge Control Register (offset = 40h) [reset = X]
      19. 8.13.19 DISCHCTRL2: 2nd Discharge Control Register (offset = 41h) [reset = X]
      20. 8.13.20 DISCHCTRL3: 3rd Discharge Control Register (offset = 42h) [reset = X]
      21. 8.13.21 PG_DELAY1: 1st Power Good Delay Register (offset = 43h) [reset = X]
      22. 8.13.22 FORCESHUTDN: Force Emergency Shutdown Control Register (offset = 91h) [reset = 0000 0000]
      23. 8.13.23 BUCK1SLPCTRL: BUCK1 Sleep Control Register (offset = 92h) [reset = X]
      24. 8.13.24 BUCK2SLPCTRL: BUCK2 Sleep Control Register (offset = 93h) [reset = X]
      25. 8.13.25 BUCK4VID: BUCK4 VID Register (offset = 94h) [reset = X]
      26. 8.13.26 BUCK4SLPVID: BUCK4 Sleep VID Register (offset = 95h) [reset = X]
      27. 8.13.27 BUCK5VID: BUCK5 VID Register (offset = 96h) [reset = X]
      28. 8.13.28 BUCK5SLPVID: BUCK5 Sleep VID Register (offset = 97h) [reset = X]
      29. 8.13.29 BUCK6VID: BUCK6 VID Register (offset = 98h) [reset = X]
      30. 8.13.30 BUCK6SLPVID: BUCK6 Sleep VID Register (offset = 99h) [reset = X]
      31. 8.13.31 LDOA2VID: LDOA2 VID Register (offset = 9Ah) [reset = X]
      32. 8.13.32 LDOA3VID: LDOA3 VID Register (offset = 9Bh) [reset = X]
      33. 8.13.33 BUCK123CTRL: BUCK1-3 Control Register (offset = 9Ch) [reset = X]
      34. 8.13.34 PG_DELAY2: 2nd Power Good Delay Register (offset = 9Dh) [reset = X]
      35. 8.13.35 SWVTT_DIS: SWVTT Disable Register (offset = 9Fh) [reset = X]
      36. 8.13.36 I2C_RAIL_EN1: 1st VR Pin Enable Override Register (offset = A0h) [reset = X]
      37. 8.13.37 I2C_RAIL_EN2/GPOCTRL: 2nd VR Pin Enable Override and GPO Control Register (offset = A1h) [reset = X]
      38. 8.13.38 PWR_FAULT_MASK1: 1st VR Power Fault Mask Register (offset = A2h) [reset = X]
      39. 8.13.39 PWR_FAULT_MASK2: 2nd VR Power Fault Mask Register (offset = A3h) [reset = X]
      40. 8.13.40 GPO1PG_CTRL1: 1st GPO1 PG Control Register (offset = A4h) [reset = X]
      41. 8.13.41 GPO1PG_CTRL2: 2nd GPO1 PG Control Register (offset = A5h) [reset = X]
      42. 8.13.42 GPO4PG_CTRL1: 1st GPO4 PG Control Register (offset = A6h) [reset = X]
      43. 8.13.43 GPO4PG_CTRL2: 2nd GPO4 PG Control Register (offset = A7h) [reset = X]
      44. 8.13.44 GPO2PG_CTRL1: 1st GPO2 PG Control Register (offset = A8h) [reset = X]
      45. 8.13.45 GPO2PG_CTRL2: 2nd GPO2 PG Control Register (offset = A9h) [reset = X]
      46. 8.13.46 GPO3PG_CTRL1: 1st GPO3 PG Control Register (offset = AAh) [reset = X]
      47. 8.13.47 GPO3PG_CTRL2: 2nd GPO3 PG Control Register (offset = ABh) [reset = X]
      48. 8.13.48 MISCSYSPG Register (offset = ACh) [reset = X]
        1. 8.13.48.1 VTT_DISCH_CTRL Register (offset = ADh) [reset = X]
      49. 8.13.49 LDOA1_SWB2_CTRL: LDOA1 and SWB2 Control Register (offset = AEh) [reset = X]
      50. 8.13.50 PG_STATUS1: 1st Power Good Status Register (offset = B0h) [reset = 0000 0000]
      51. 8.13.51 PG_STATUS2: 2nd Power Good Status Register (offset = B1h) [reset = 0000 0000]
      52. 8.13.52 PWR_FAULT_STATUS1: 1st Power Fault Status Register (offset = B2h) [reset = 0000 0000]
      53. 8.13.53 PWR_FAULT_STATUS2: 2nd Power Fault Status Register (offset = B3h) [reset = 0000 0000]
      54. 8.13.54 TEMPCRIT: Temperature Fault Status Register (offset = B4h) [reset = 0000 0000]
      55. 8.13.55 TEMPHOT: Temperature Hot Status Register (offset = B5h) [reset = 0000 0000]
      56. 8.13.56 OC_STATUS: Overcurrent Fault Status Register (offset = B6h) [reset = 0000 0000]
  9. 9 Applications, Implementation, and Layout
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Controller Design Procedure
          1. 9.2.2.1.1 Selecting the Inductor
          2. 9.2.2.1.2 Selecting the Output Capacitors
          3. 9.2.2.1.3 Selecting the FETs
          4. 9.2.2.1.4 Bootstrap Capacitor
          5. 9.2.2.1.5 Setting the Current Limit
          6. 9.2.2.1.6 Selecting the Input Capacitors
        2. 9.2.2.2 Converter Design Procedure
          1. 9.2.2.2.1 Selecting the Inductor
          2. 9.2.2.2.2 Selecting the Output Capacitors
          3. 9.2.2.2.3 Selecting the Input Capacitors
        3. 9.2.2.3 LDO Design Procedure
      3. 9.2.3 Application Curves
      4. 9.2.4 Layout
        1. 9.2.4.1 Layout Guidelines
        2. 9.2.4.2 Layout Example
      5. 9.2.5 VIN 5-V Application
        1. 9.2.5.1 Design Requirements
        2. 9.2.5.2 Design Procedure
        3. 9.2.5.3 Application Curves
    3. 9.3 Power Supply Coupling and Bulk Capacitors
    4. 9.4 Do's and Don'ts
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Development Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.13.1 Register Map Summary

Do not attempt to write a RESERVED R/W bit to the opposite value. When the reset value of a bit register is 0bX, it means the bit value is coming from the OTP memory.

Table 8-26 Register Map Summary
AddressNameShort Description
00hDEVICEID1Device ID code indicating revision
01hDEVICEID2Device ID code indicating revision
02hIRQInterrupt statuses
03hIRQ_MASKInterrupt masking
04hPMIC_STATPMIC temperature indicator
05hSHUTDNSRCShutdown root cause indicator bits
20hBUCK1CTRLBUCK1 decay control and voltage select
21hBUCK2CTRLBUCK2 decay control and voltage select
22hBUCK3DECAYBUCK3 decay control
23hBUCK3VIDBUCK3 voltage select
24hBUCK3SLPCTRLBUCK3 voltage select for sleep state
25hBUCK4CTRLBUCK4 control
26hBUCK5CTRLBUCK5 control
27hBUCK6CTRLBUCK6 control
28hLDOA2CTRLLDOA2 control
29hLDOA3CTRLLDOA3 control
40hDISCHCTRL1Discharge resistors for each rail control
41hDISCHCTRL2Discharge resistors for each rail control
42hDISCHCTRL3Discharge resistors for each rail control
43hPG_DELAY1System Power Good on GPO3 (if GPO3 is programmed to be system PG)
91hFORCESHUTDNSoftware force shutdown
92hBUCK1SLPCTRLBUCK1 voltage select for sleep state
93hBUCK2SLPCTRLBUCK2 voltage select for sleep state
94hBUCK4VIDBUCK4 voltage select
95hBUCK4SLPVIDBUCK4 voltage select for sleep state
96hBUCK5VIDBUCK5 voltage select
97hBUCK5SLPVIDBUCK5 voltage select for sleep state
98hBUCK6VIDBUCK6 voltage select
99hBUCK6SLPVIDBUCK6 voltage select for sleep state
9AhLDOA2VIDLDOA2 voltage select
9BhLDOA3VIDLDOA3 voltage select
9ChBUCK123CTRLBUCK1, 2, and 3 disable and PFM/PWM mode control
9DhPG_DELAY2System Power Good on GPO1, 2, and 4 (if GPOs are programmed to be system PG)
9FhSWVTT_DIS SWs and VTT I2C disable bits
A0hI2C_RAIL_EN1I2C Enable control of individual rails
A1hI2C_RAIL_EN2/GPOCTRLI2C Enable control of individual rails and I2C controlled GPOs, high or low
A2hPWR_FAULT_MASK1Power fault masking for individual rails
A3hPWR_FAULT_MASK2Power fault masking for individual rails
A4hGPO1PG_CTRL1Power good tree control for GPO1
A5hGPO1PG_CTRL2Power good tree control for GPO1
A6hGPO4PG_CTRL1Power good tree control for GPO4
A7hGPO4PG_CTRL2Power good tree control for GPO4
A8hGPO2PG_CTRL1Power good tree control for GPO2
A9hGPO2PG_CTRL2Power good tree control for GPO2
AAhGPO3PG_CTRL1Power good tree control for GPO3
ABhGPO3PG_CTRL2Power good tree control for GPO3
AChMISCSYSPGPower good tree control with CTL3 and CTL6 for GPO
ADhVTT_DISCH_CTRLDischarge resistor setting for VTT LDO
AEhLDOA1_SWB2_CTRLLDOA1 and SWB2 control for discharge, voltage selection, and enable
B0hPG_STATUS1Power good statuses for individual rails
B1hPG_STATUS2Power good statuses for individual rails
B2hPWR_FAULT_STATUS1Power fault statuses for individual rails
B3hPWR_FAULT_STATUS2Power fault statuses for individual rails
B4hTEMPCRITCritical temperature indicators
B5hTEMPHOTHot temperature indicators

Complex bit access types are encoded to fit into small table cells. Table 8-27 shows the codes that are used for access types in this section.

Table 8-27 Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite