SWCS138E June 2017 – December 2022 TPS650864
PRODUCTION DATA
Do not attempt to write a RESERVED R/W bit to the opposite value. When the reset value of a bit register is 0bX, it means the bit value is coming from the OTP memory.
Address | Name | Short Description |
---|---|---|
00h | DEVICEID1 | Device ID code indicating revision |
01h | DEVICEID2 | Device ID code indicating revision |
02h | IRQ | Interrupt statuses |
03h | IRQ_MASK | Interrupt masking |
04h | PMIC_STAT | PMIC temperature indicator |
05h | SHUTDNSRC | Shutdown root cause indicator bits |
20h | BUCK1CTRL | BUCK1 decay control and voltage select |
21h | BUCK2CTRL | BUCK2 decay control and voltage select |
22h | BUCK3DECAY | BUCK3 decay control |
23h | BUCK3VID | BUCK3 voltage select |
24h | BUCK3SLPCTRL | BUCK3 voltage select for sleep state |
25h | BUCK4CTRL | BUCK4 control |
26h | BUCK5CTRL | BUCK5 control |
27h | BUCK6CTRL | BUCK6 control |
28h | LDOA2CTRL | LDOA2 control |
29h | LDOA3CTRL | LDOA3 control |
40h | DISCHCTRL1 | Discharge resistors for each rail control |
41h | DISCHCTRL2 | Discharge resistors for each rail control |
42h | DISCHCTRL3 | Discharge resistors for each rail control |
43h | PG_DELAY1 | System Power Good on GPO3 (if GPO3 is programmed to be system PG) |
91h | FORCESHUTDN | Software force shutdown |
92h | BUCK1SLPCTRL | BUCK1 voltage select for sleep state |
93h | BUCK2SLPCTRL | BUCK2 voltage select for sleep state |
94h | BUCK4VID | BUCK4 voltage select |
95h | BUCK4SLPVID | BUCK4 voltage select for sleep state |
96h | BUCK5VID | BUCK5 voltage select |
97h | BUCK5SLPVID | BUCK5 voltage select for sleep state |
98h | BUCK6VID | BUCK6 voltage select |
99h | BUCK6SLPVID | BUCK6 voltage select for sleep state |
9Ah | LDOA2VID | LDOA2 voltage select |
9Bh | LDOA3VID | LDOA3 voltage select |
9Ch | BUCK123CTRL | BUCK1, 2, and 3 disable and PFM/PWM mode control |
9Dh | PG_DELAY2 | System Power Good on GPO1, 2, and 4 (if GPOs are programmed to be system PG) |
9Fh | SWVTT_DIS | SWs and VTT I2C disable bits |
A0h | I2C_RAIL_EN1 | I2C Enable control of individual rails |
A1h | I2C_RAIL_EN2/GPOCTRL | I2C Enable control of individual rails and I2C controlled GPOs, high or low |
A2h | PWR_FAULT_MASK1 | Power fault masking for individual rails |
A3h | PWR_FAULT_MASK2 | Power fault masking for individual rails |
A4h | GPO1PG_CTRL1 | Power good tree control for GPO1 |
A5h | GPO1PG_CTRL2 | Power good tree control for GPO1 |
A6h | GPO4PG_CTRL1 | Power good tree control for GPO4 |
A7h | GPO4PG_CTRL2 | Power good tree control for GPO4 |
A8h | GPO2PG_CTRL1 | Power good tree control for GPO2 |
A9h | GPO2PG_CTRL2 | Power good tree control for GPO2 |
AAh | GPO3PG_CTRL1 | Power good tree control for GPO3 |
ABh | GPO3PG_CTRL2 | Power good tree control for GPO3 |
ACh | MISCSYSPG | Power good tree control with CTL3 and CTL6 for GPO |
ADh | VTT_DISCH_CTRL | Discharge resistor setting for VTT LDO |
AEh | LDOA1_SWB2_CTRL | LDOA1 and SWB2 control for discharge, voltage selection, and enable |
B0h | PG_STATUS1 | Power good statuses for individual rails |
B1h | PG_STATUS2 | Power good statuses for individual rails |
B2h | PWR_FAULT_STATUS1 | Power fault statuses for individual rails |
B3h | PWR_FAULT_STATUS2 | Power fault statuses for individual rails |
B4h | TEMPCRIT | Critical temperature indicators |
B5h | TEMPHOT | Hot temperature indicators |
Complex bit access types are encoded to fit into small table cells. Table 8-27 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |