One of the main benefits from the 180° interleaving of phases is significant reductions in the high-frequency ripple components of both the input current and the current into the output capacitor of the PFC preregulator. Compared to that of a single-phase PFC stage of equal power, the reduced ripple on the input current eases the burden of filtering conducted-EMI noise and helps reduce the EMI filter and C_IN sizes. Additionally, reduced high-frequency ripple current into the PFC output capacitor, C_OUT, helps to reduce its size and cost. Furthermore, with reduced ripple and average current in each phase, the boost inductor size can be smaller than in a single-phase design [3].

Ripple current reduction due to interleaving is often referred to as ripple cancellation, but strictly speaking, the peak-to-peak ripple is completely cancelled only at 50% duty-cycle in a 2-phase system. At duty-cycles other than 50%, ripple reduction occurs in the form of partial cancellation due to the superposition of the individual phase currents. Nevertheless, compared to the ripple currents of an equivalent single-phase PFC preregulator, those of a 2-phase interleaved design are extraordinarily smaller [3]. Independent of ripple cancellation, the frequency of the interleaved ripple, at both the input and output, is 2 × f_PWM.

At the PFC input, 180° interleaving reduces the peak-to-peak current-ripple amplitude to ½ or less of the ripple amplitude of the equivalent single-phase current.

At the PFC output, 180° interleaving reduces the rms value of the PFC-generated ripple current in the output capacitor by a factor of slightly more than √ 2, for PWM duty-cycles > 50%.

This can be seen in the following derivations, adapting the method by Erickson [4].

In a single-phase PFC preregulator, the total rms capacitor current contributed by the PFC stage at all duty-cycles can be shown to be approximated by:

Equation 1.

where

• I_O is the average PFC output load current
• V_O is the average PFC output voltage
• V_M is the peak of the input AC-line voltage
• η is the efficiency of the PFC stage at these conditions

In a dual-phase interleaved PFC preregulator, the total rms capacitor current contributed by the PFC stage for D > 50% can be shown to be approximated by:

Equation 2.

It can be seen that the quantity under the radical for i_CRMS2φ is slightly smaller than ½ of that under the radical for i_CRMS1φ. The rms currents shown contain both the low-frequency and the high-frequency components of the PFC output current. Interleaving reduces the high-frequency component, but not the low-frequency component.