JAJSRW8 November   2023 ADC34RF55

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics - Power Consumption
    6. 5.6  Electrical Characteristics - DC Specifications
    7. 5.7  Electrical Characteristics - AC Specifications (Dither DISABLED)
    8. 5.8  Electrical Characteristics - AC Specifications (Dither ENABLED)
    9. 5.9  Timing Requirements
    10. 5.10 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Inputs
        1. 6.3.1.1 Input Bandwidth and Full-Scale
        2. 6.3.1.2 Input Imbalance
        3. 6.3.1.3 Over Range Indication
        4. 6.3.1.4 Analog out-of-band dither
      2. 6.3.2 Sampling Clock Input
      3. 6.3.3 ADC Foreground Calibration
        1. 6.3.3.1 Calibration Control
        2. 6.3.3.2 ADC Switch
        3. 6.3.3.3 Calibration Configuration
      4. 6.3.4 SYSREF
        1. 6.3.4.1 SYSREF Capture Detection
      5. 6.3.5 Decimation Filter
        1. 6.3.5.1 Decimation Filter Response
        2. 6.3.5.2 Decimation Filter Configuration
        3. 6.3.5.3 20-bit Output Mode
        4. 6.3.5.4 Numerically Controlled Oscillator (NCO)
        5. 6.3.5.5 NCO Frequency Programming Using the SPI Interface
        6. 6.3.5.6 Fast Frequency Hopping
          1. 6.3.5.6.1 Fast frequency hopping using the GPIO1/2 pins
          2. 6.3.5.6.2 Fast frequency hopping using GPIO1/2, SEN and SDATA pins
          3. 6.3.5.6.3 Fast frequency hopping using the fast SPI
      6. 6.3.6 JESD204B Interface
        1. 6.3.6.1 JESD204B Initial Lane Alignment (ILA)
          1. 6.3.6.1.1 SYNC Signal
        2. 6.3.6.2 JESD204B Frame Assembly
          1. 6.3.6.2.1 JESD204B Frame Assembly in Bypass Mode
          2. 6.3.6.2.2 JESD204B Frame Assembly with Real Decimation - Single Band
          3. 6.3.6.2.3 JESD204B Frame Assembly with Complex Decimation - Single Band
          4. 6.3.6.2.4 JESD204B Frame Assembly with Decimation - Dual Band
        3. 6.3.6.3 SERDES Output MUX
      7. 6.3.7 Test Pattern
        1. 6.3.7.1 Transport Layer
        2. 6.3.7.2 Link Layer
        3. 6.3.7.3 Internal Capture Memory Buffer
    4. 6.4 Device Functional Modes
      1. 6.4.1 Bypass Mode
      2. 6.4.2 Digital Averaging
    5. 6.5 Programming
      1. 6.5.1 GPIO Pin Control
      2. 6.5.2 Configuration using the SPI interface
        1. 6.5.2.1 Register Write
        2. 6.5.2.2 Register Read
    6. 6.6 Register Maps
      1. 6.6.1 Detailed Register Description
  8. 7 Application Information Disclaimer
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Wideband RF Sampling Receiver
      2. 7.2.2 Design Requirements
        1. 7.2.2.1 Input Signal Path
        2. 7.2.2.2 Clocking
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1 Sampling Clock
      4. 7.2.4 Application Curves
    3. 7.3 Initialization Set Up
      1. 7.3.1 Initial Device Configuration After Power-Up
        1. 7.3.1.1  STEP 1: RESET
        2. 7.3.1.2  STEP 2: Device Configuration
        3. 7.3.1.3  STEP 3: JESD Interface Configuration (1)
        4. 7.3.1.4  STEP 4: SYSREF Synchronization
        5. 7.3.1.5  STEP 5: JESD Interface Configuration (2)
        6. 7.3.1.6  STEP 6: Analog Trim Settings
        7. 7.3.1.7  STEP 7: Calibration Configuration
        8. 7.3.1.8  STEP 8: SYSREF Synchronization
        9. 7.3.1.9  STEP 9: Run Power up Calibration
        10. 7.3.1.10 Step 10: JESD Interface Synchronization
        11. 7.3.1.11 Step 11: NCO Configuration
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 デバイスのサポート
      1. 8.1.1 サード・パーティ製品に関する免責事項
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.4 Power Supply Recommendations

The ADC34RF5x requires four different power-supplies. The AVDD18, AVDD12 and CLKVDD rail provides power for the internal analog and clocking circuits of the ADC while the DVDD rail powers the digital logic (including averaging and decimation filter) and the JESD204B digital interface.

Power sequencing is required as shown in Initialization Set Up. The AVDD18, AVDD12 and especially the CLKVDD power supply must be low noise to achieve data sheet performance. For applications operating near DC, the 1/f noise contribution of the power supply must also be considered.

Power supply decoupling capacitors (0.1 μF) must be as close as possible to the pins on the top layer.

GUID-20211021-SS0I-PGCL-CLL9-QNBRFJ0X6BWT-low.svg Figure 7-5 Power supply rejection ratio (PSRR) vs frequency

The recommended power supply architecture for a low noise design is to first use a high-efficiency step down switching regular, followed by a second stage of regulation using a low noise LDO for each power rail as shown in Figure 7-6. This provides additional switching noise reduction and improved voltage accuracy.

TI WEBENCH® Power Designer can be used to select and design the individual power-supply elements. Recommended switching regulators for the first stage include the LMS3635, and similar devices. Recommended low dropout (LDO) linear regulators include the TPS7A8400, and similar devices.

GUID-20211021-SS0I-QZHK-QW96-25WK0JP3L9XP-low.svg Figure 7-6 Power supply design example

AVDD12 or CLKVDD should not be shared with the DVDD to prevent digital switching noise from coupling into the analog domain.