JAJSHV5B June   2017  – August 2019 ADS1287

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      機能ブロック図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Noise Performance
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Analog Input and Multiplexer
      2. 9.3.2 Programmable Gain Amplifier (PGA)
      3. 9.3.3 Modulator
        1. 9.3.3.1 Modulator Overrange
      4. 9.3.4 Voltage Reference Inputs (REFP, REFN)
      5. 9.3.5 Digital Filter
        1. 9.3.5.1 Sinc Filter Stage
        2. 9.3.5.2 FIR Filter Stage
        3. 9.3.5.3 Group Delay and Step Response
          1. 9.3.5.3.1 Linear Phase Response
          2. 9.3.5.3.2 Minimum Phase Response
        4. 9.3.5.4 HPF Stage
      6. 9.3.6 Reset (RESET Pin and Reset Command)
      7. 9.3.7 Master Clock Input (CLK)
    4. 9.4 Device Functional Modes
      1. 9.4.1  Operational Mode
      2. 9.4.2  Chop Mode
      3. 9.4.3  Offset
      4. 9.4.4  Power-Down Mode
      5. 9.4.5  Standby Mode
      6. 9.4.6  Synchronization
        1. 9.4.6.1 Pulse-Sync Mode
        2. 9.4.6.2 Continuous-Sync Mode
      7. 9.4.7  Reading Data
        1. 9.4.7.1 Read-Data-Continuous Mode (RDATAC)
        2. 9.4.7.2 Stop-Read-Data-Continuous-Mode (SDATAC)
      8. 9.4.8  Conversion Data Format
      9. 9.4.9  Offset and Full-Scale Calibration Registers
        1. 9.4.9.1 OFC[2:0] Registers
        2. 9.4.9.2 FSC[2:0] Registers
      10. 9.4.10 Calibration Command
        1. 9.4.10.1 OFSCAL Command
        2. 9.4.10.2 GANCAL Command
      11. 9.4.11 User Calibration
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Chip Select (CS)
        2. 9.5.1.2 Serial Clock (SCLK)
        3. 9.5.1.3 Data Input (DIN)
        4. 9.5.1.4 Data Output (DOUT)
        5. 9.5.1.5 Serial Interface Timeout
        6. 9.5.1.6 Data Ready (DRDY)
      2. 9.5.2 Commands
        1. 9.5.2.1  WAKEUP: Wake Up Command
        2. 9.5.2.2  STANDBY: Standby Mode Command
        3. 9.5.2.3  SYNC: Synchronize ADC Conversions
        4. 9.5.2.4  RESET: Reset Command
        5. 9.5.2.5  RDATAC: Read Data Continuous Mode Command
        6. 9.5.2.6  SDATAC: Stop Read Data Continuous Mode Command
        7. 9.5.2.7  RDATA: Read Data Command
        8. 9.5.2.8  RREG: Read Register Data Command
        9. 9.5.2.9  WREG: Write Register Data Command
        10. 9.5.2.10 OFSCAL: Offset Calibration Command
        11. 9.5.2.11 GANCAL: Gain Calibration Command
    6. 9.6 Register Map
      1. 9.6.1 Register Descriptions
        1. 9.6.1.1 ID/CFG: ID, Configuration Register (address = 00h) [reset = x0h]
          1. Table 22. ID/CFG Register Field Descriptions
        2. 9.6.1.2 CONFIG0: Configuration Register 0 (address = 01h) [reset = 52h]
          1. Table 23. CONFIG0 Register Field Descriptions
        3. 9.6.1.3 CONFIG1: Configuration Register 1 (address = 02h) [reset = 08h]
          1. Table 24. CONFIG1 Register Field Descriptions
        4. 9.6.1.4 High-Pass Filter Corner Frequency (HPFx) Registers (address = 03h, 04h) [reset = 32h, 03h]
          1. Table 25. HPF0, HPF1 Registers Field Description
        5. 9.6.1.5 Offset Calibration (OFCx) Registers (address = 05h, 06h, 07h) [reset = 00h, 00h, 00h]
          1. Table 26. OFC0, OFC1, OFC2 Registers Field Description
        6. 9.6.1.6 Full-Scale Calibration (FSCx) Registers (address = 08h, 09h, 0Ah) [reset = 00h, 00h, 40h]
          1. Table 27. FSC0, FSC1, FSC2 Registers Field Description
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Geophone Application
      2. 10.2.2 Digital Interface
    3. 10.3 Initialization Set Up
  11. 11Power Supply Recommendations
    1. 11.1 Analog Power Supplies
    2. 11.2 Digital Power Supply
    3. 11.3 Power-Supply Sequence
  12. 12Layout
    1. 12.1 Layout Guidelines
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントの更新通知を受け取る方法
    2. 13.2 コミュニティ・リソース
    3. 13.3 商標
    4. 13.4 静電気放電に関する注意事項
    5. 13.5 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RHF|24
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

maximum and minimum specifications apply from –40°C to +85°C; typical specifications are at 25°C; all specifications are at AVDD = 2.5 V, AVSS = –2.5 V, DVDD = 3.3 V, f(CLK) = 1.024 MHz, V(REFP) = 0 V, V(REFN) = –2.5 V, gain = 1, high-resolution and low-power modes, chop enabled, and fDATA = 1000 SPS (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
Input current Chop disabled 10 pA
Chop enabled 50
Input resistance Common-mode, chop disabled 50 GΩ
Differential-mode, chop disabled 100
Differential-mode, chop enabled 20
Input capacitance Common-mode 20 pF
Differential-mode 5
PGA
Voltage noise density High-resolution mode 15 nV/√Hz
Low-power mode 25
1/f noise corner Chop disabled 25 Hz
Gain factors 1, 2, 4, 8, 16 V/V
Differential output impedance Nominal 1.7 kΩ
Tolerance –15% 15%
PGA output capacitor 10 nF
ADC
Resolution FIR filter mode 31 Bits
Voltage noise density High-resolution mode 190 nV/√Hz
Low-power mode 275
fDATA Data rate FIR filter mode 62.5, 125, 250, 500, 1000 SPS
SYSTEM PERFORMANCE
SNR Signal-to-noise ratio
(see Table 1 through Table 4)		 High-resolution mode, gain = 1 110 113 dB
High-resolution mode, gain = 2 110 113
High-resolution mode, gain = 4 108 113
High-resolution mode, gain = 8 107 112
High-resolution mode, gain = 16 105 110
Low-power mode, gain = 1 106 110
THD Total harmonic distortion(2) Gain = 1 –115 –105 dB
Gain = 2, 4, 8, and 16 –115
SFDR Spurious-free dynamic range 115 dB
VIO Input offset voltage TA = 25°C –300 ±50 300 µV
Chop disabled, TA = 25°C ±300
After calibration(3) ±1
Input offset voltage drift 0.05 µV/°C
Chop disabled 1
Gain error High-resolution mode, TA = 25°C –0.8% –0.3% 0.2%
Low-power mode, TA = 25°C –0.6% –0.1% 0.4%
Gain error after calibration(3) 0.0005%
Gain drift All gains 1 ppm/°C
Gain match All gains relative to gain = 1 –0.5% ±0.1% 0.5%
Calibration margin(1) –106% 106%
SYSTEM PERFORMANCE, continued
CMRR Common-mode rejection ratio High-resolution mode, DC to 60 Hz 100 115 dB
Low-resolution mode, DC to 60 Hz 95 110
PSRR Power-supply rejection ratio Analog supplies, DC to 60 Hz 75 90 dB
Digital supply, DC to 60 Hz 90 105
VOLTAGE REFERENCE INPUT
Input impedance High-resolution mode 320 kΩ
Low-power mode 640
DIGITAL FILTER RESPONSE
Pass-band ripple ±0.003 dB
Pass band (–0.01 dB) 0.375 × f(DATA) Hz
Bandwidth (–3 dB) 0.413 × f(DATA) Hz
High-pass filter corner 0.1 10 Hz
Stop-band attenuation(4) 135 dB
Stop band 0.500 × fDATA Hz
Group delay Minimum phase filter 5 / fDATA s
Linear phase filter 31 / fDATA
Settling time (latency) Minimum phase filter 62 / fDATA s
Linear phase filter 62 / fDATA
DIGITAL INPUT/OUTPUTS
VIL Logic input level, low DGND 0.2 × DVDD V
VIH Logic input level, high 0.8 × DVDD DVDD V
VOL Logic output level, low IOL = 1 mA DGND 0.2 × DVDD V
VOH Logic output level, high IOH = 1 mA 0.8 × DVDD DVDD V
Input current 0 ≤ VDIGITAL IN ≤ DVDD –10 10 μA
POWER SUPPLY
IAVDD,
IAVSS 		Analog supply current High-resolution mode 750 1100 µA
Low-power mode 330 480
Standby mode 1
Power-down mode 1
IDVDD Digital supply current High-resolution mode 240 320 µA
Low-power mode 220 300
Standby mode(5) 25
Power-down mode(5) 1
PD Power dissipation High-resolution mode 4.5 6.6 mW
Low-power mode 2.4 3.4
Standby mode(5) 90 µW
Power-down mode(5) 10
(1) Calibration margin is the maximum allowed input voltage range after calibration operations.
(2) Test signal: 31.25 Hz, –0.5 dBFS.
(3) Calibration accuracy is on the level of noise reduced by four (calibration averages 16 readings).
(4) Input frequencies are in the range of N × f(CLK) / 1024 ± f(DATA) / 2 (where N = 1, 2, 3, and so forth) intermodulated with the modulator chopper clock. At these frequencies, intermodulation components are –120 dBFS (typ).
(5) CLK input stopped.