JAJSPF5 April   2024 ADS9813

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Inputs
        1. 6.3.1.1 Input Clamp Protection Circuit
        2. 6.3.1.2 Programmable Gain Amplifier (PGA)
        3. 6.3.1.3 Wide-Common-Mode Voltage Rejection Circuit
      2. 6.3.2 ADC Transfer Function
      3. 6.3.3 ADC Sampling Clock Input
      4. 6.3.4 Synchronizing Multiple ADCs
      5. 6.3.5 Reference Voltage
      6. 6.3.6 Test Patterns for Data Interface
        1. 6.3.6.1 Fixed Pattern
        2. 6.3.6.2 Digital Ramp
        3. 6.3.6.3 Alternating Test Pattern
    4. 6.4 Device Functional Modes
      1. 6.4.1 Reset
      2. 6.4.2 Power-Down
      3. 6.4.3 Initialization Sequence
      4. 6.4.4 Normal Operation
    5. 6.5 Programming
      1. 6.5.1 Register Write
      2. 6.5.2 Register Read
      3. 6.5.3 Multiple Devices in a Daisy-Chain Topology for SPI Configuration
        1. 6.5.3.1 Register Write With Daisy-Chain
        2. 6.5.3.2 Register Read With Daisy-Chain
  8. 7 Register Map
    1. 7.1 Register Bank 0
    2. 7.2 Register Bank 1
    3. 7.3 Register Bank 2
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Parametric Measurement Unit (PMU)
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Mechanical Data

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3 Register Bank 2

Figure 7-47 Register Bank 2 Map
ADD D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
22h INIT_2
23h INIT_3
26h INIT_4
Table 7-3 Register Section/Block Access Type Codes
Access Type Code Description
R R Read
W W Write
R/W R/W Read or write
Reset or Default Value
-n Value after reset or the default value

7.3.1 Register 22h (offset = 22h) [reset = 0h]

Figure 7-48 Register 22h
15 14 13 12 11 10 9 8
INIT_2
R/W-0h
7 6 5 4 3 2 1 0
INIT_2
R/W-0h
Figure 7-49 Register 12 Field Descriptions
Bit Field Type Reset Description
15-0 INIT_2 R/W 0h INIT_2 field for device initialization. Write 0x0079 during initialization sequence. See Initialization Sequence.

7.3.2 Register 23h (offset = 23h) [reset = 0h]

Figure 7-50 Register 23h
15 14 13 12 11 10 9 8
INIT_3
R/W-0h
7 6 5 4 3 2 1 0
INIT_3
R/W-0h
Figure 7-51 Register 23 Field Descriptions
Bit Field Type Reset Description
15-0 INIT_3 R/W 0h INIT_3 field for device initialization. Write 0xE000 during initialization sequence. See Initialization Sequence.

7.3.3 Register 26h (offset = 26h) [reset = 0h]

Figure 7-52 Register 26h
15 14 13 12 11 10 9 8
INIT_4
R/W-0h
7 6 5 4 3 2 1 0
INIT_4
R/W-0h
Figure 7-53 Register 26h Field Descriptions
Bit Field Type Reset Description
15-0 INIT_4 R/W 0h INIT_4 field for device initialization. Write 0x0040 during initialization sequence. See Initialization Sequence.