JAJSPF5 April 2024 ADS9813
ADVANCE INFORMATION
ADD | D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0Dh | RESERVED | DATA_FORMAT | RESERVED | GE_CAL_EN1 | RESERVED | |||||||||||
12h | RESERVED | XOR_PRBS | XOR_EN | RESERVED | ||||||||||||
13h | RESERVED | RAMP_INC_A | TP_MODE_A | TP_EN_A | RESERVED | |||||||||||
14h | TP0_A | |||||||||||||||
15h | TP1_A | TP0_A | ||||||||||||||
16h | TP1_A | |||||||||||||||
18h | RESERVED | RAMP_INC_B | TP_MODE_B | TP_EN_B | RESERVED | |||||||||||
19h | TP0_B | |||||||||||||||
1Ah | TP1_B | TP0_B | ||||||||||||||
1Bh | TP1_B | |||||||||||||||
1Ch | RESERVED | USER_BITS_CH[8:5] | RESERVED | USER_BITS_CH[4:1] | ||||||||||||
C0h | RESERVED | ANA_BW | PD_CH | |||||||||||||
C1h | RESERVED | PD_REF | RESERVED | DATA_RATE | RESERVED | |||||||||||
C2h | RANGE_CH4 | RANGE_CH3 | RANGE_CH2 | RANGE_CH1 | ||||||||||||
C3h | RANGE_CH8 | RANGE_CH7 | RANGE_CH6 | RANGE_CH5 | ||||||||||||
C4h | RESERVED | CM_RNG_CH[8:5] | CM_RNG_CH[4:1] | RESERVED | CM_EN_CH[8:5] | CM_EN_CH[4:1] | RESERVED | PD_CHIP | ||||||||
C5h | RESERVED | CM_CTRL_EN | RESERVED |
Access Type | Code | Description |
---|---|---|
R | R | Read |
W | W | Write |
R/W | R/W | Read or write |
Reset or Default Value | ||
-n | Value after reset or the default value |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | DATA_FORMAT | RESERVED | |||||
R/W-0h | R/W-1h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GE_CAL_EN1 | RESERVED | ||||||
R/W-0h | R/W-2h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-14 | RESERVED | R/W | 0h | Reserved. Do not change from the default reset value. |
13 | DATA_FORMAT | R/W | 1h | Select data format for the
ADC conversion result. 0 : Straight binary format 1 : Two's-complement format |
12-8 | RESERVED | R/W | 0h | Reserved. Do not change from the default reset value. |
7 | GE_CAL_EN1 | R/W | 0h | Global control for gain
error calibration. 0 : Gain error calibration disabled for all channels 1 : Gain error calibration enabled for all channels |
6-0 | RESERVED | R/W | 2h | Reserved. Do not change from the default reset value. |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | XOR_PRBS | XOR_EN | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-2h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-5 | RESERVED | R/W | 0h | Reserved. Do not change from the default reset value. |
4 | XOR_PRBS | R/W | 0h | Select bit for XOR operation when XOR_EN =
1b. 0 : PRBS is appended after the LSB of the ADC conversion result. The ADC conversion result is bit-wise XOR with the PRBS bit. 1 : The ADC conversion result is bit-wise XOR with the LSB of the ADC conversion result. |
3 | XOR_EN | R/W | 0h | Enables XOR operation on
the ADC conversion result. 0 : XOR operation is disabled 1 : Bit-wise XOR operation on ADC conversion result is enabled |
2-0 | RESERVED | R/W | 2h | Reserved. Do not change from the default reset value. |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAMP_INC_A | TP_MODE_A | TP_EN_A | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | RESERVED | R/W | 0h | Reserved. Do not change from the default reset value. |
7-4 | RAMP_INC_A | R/W | 0h | Increment value for the
ramp pattern output. The output ramp increments by N+1, where N is
the value configured in this register. |
3-2 | TP_MODE_A | R/W | 0h | Select digital test pattern for analog input
channels 1, 2, 3, and 4. 0 : Fixed pattern from the TP0_A register 1 : Fixed pattern from the TP0_A register 2 : Digital ramp output 3 : Alternate fixed pattern output from the TP0_A and TP1_A registers |
1 | TP_EN_A | R/W | 0h | Enable digital test pattern for data
corresponding to channels 1, 2, 3, and 4. 0 : Data output is the ADC conversion result 1 : Data output is the digital test pattern for channels 1, 2, 3, and 4 |
0 | RESERVED | R/W | 0h | Reserved. Do not change from the default reset value. |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TP0_A[15:0] | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TP0_A[15:0] | |||||||
R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | TP0_A[15:0] | R/W | 0h | Lower 16 bits of test
pattern 0 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TP1_A[7:0] | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TP0_A[23:16] | |||||||
R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | TP1_A[7:0] | R/W | 0h | Lower eight bits of test
pattern 1 |
7-0 | TP0_A[23:16] | R/W | 0h | Upper eight bits of test
pattern 0 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TP1_A[23:8] | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TP1_A[23:8] | |||||||
R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | TP1_A[23:8] | R/W | 0h | Upper 16 bits of test
pattern 1 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAMP_INC_B | TP_MODE_B | TP_EN_B | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | RESERVED | R/W | 0h | Reserved. Do not change from the default reset value. |
7-4 | RAMP_INC_B | R/W | 0h | Increment value for the
ramp pattern output. The output ramp increments by N+1, where N is
the value configured in this register. |
3-2 | TP_MODE_B | R/W | 0h | Select digital test pattern for analog input
channels 5, 6, 7, and 8. 0 : Fixed pattern from the TP0_B register 1 : Fixed pattern from the TP0_B register 2 : Digital ramp output 3 : Alternate fixed pattern output from the TP0_B and TP1_B registers |
1 | TP_EN_B | R/W | 0h | Enable digital test pattern for data
corresponding to channels 5, 6, 7, and 8. 0 : Data output is the ADC conversion result 1 : Data output is the digital test pattern |
0 | RESERVED | R/W | 0h | Reserved. Do not change from the default reset value. |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TP0_B[15:0] | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TP0_B[15:0] | |||||||
R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | TP0_B[15:0] | R/W | 0h | Lower 16 bits of test
pattern 0 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TP1_B[7:0] | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TP0_B[23:16] | |||||||
R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | TP1_B[7:0] | R/W | 0h | Lower eight bits of test
pattern 1 |
7-0 | TP0_B[23:16] | R/W | 0h | Upper eight bits of test
pattern 0 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TP1_B[23:8] | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TP1_B[23:8] | |||||||
R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | TP1_B[23:8] | R/W | 0h | Upper 16 bits of test
pattern 1 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | USER_BITS_CH[8:5] | ||||||
R/W-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | USER_BITS_CH[4:1] | ||||||
R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | USER_BITS_CH[8:5] | R/W | 0h | User-defined bits appended
to the ADC conversion result from channels 5, 6, 7, and 8. |
7-0 | USER_BITS_CH[4:1] | R/W | 0h | User-defined bits appended
to the ADC conversion result from channels 1, 2, 3, and 4. |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | ANA_BW | ||||||
R/W-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ANA_BW | PD_CH | ||||||
R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-10 | RESERVED | R/W | 0h | Reserved. Do not change from the default reset value. |
9-2 | ANA_BW | R/W | 0h | Select analog input
bandwidth for the respective analog input channels. MSB = BW control for channel 8 LSB = BW control for channel 1 0 : Low-noise mode 1 : Wide-bandwidth mode |
1-0 | PD_CH | R/W | 0h | Power-down control for the analog input
channels. 0 : Normal operation 1 : Channels 5, 6, 7, and 8 powered down 2 : Channels 1, 2, 3, and 4 powered down 3 : All channels powered down |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | PD_REF | RESERVED | DATA_RATE | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | RESERVED | R/W | 0h | Reserved. Do not change from the default reset value. |
11 | PD_REF | R/W | 0h | ADC reference voltage
source selection. 0 : Internal reference enabled. 1 : Internal reference disabled. Connect the external reference voltage to the REFIO pin. |
10-9 | RESERVED | R/W | 0h | Reserved. Do not change from the default reset value. |
8 | DATA_RATE | R/W | 0h | Select data rate for the
data interface. 0 : Double data rate (DDR) 1 : Single data rate (SDR) |
7-0 | RESERVED | R/W | 0h | Reserved. Do not change from the default reset value. |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RANGE_CH4 | RANGE_CH3 | ||||||
R/W-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RANGE_CH2 | RANGE_CH1 | ||||||
R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | RANGE_CH4 | R/W | 0h | Select the analog input voltage range. 0 : ±5V 1 : ±3.5V 2 : ±2.5V 3 : ±7V 4 : ±10V 5 : ±12V |
11-8 | RANGE_CH3 | R/W | 0h | |
7-4 | RANGE_CH2 | R/W | 0h | |
3-0 | RANGE_CH1 | R/W | 0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RANGE_CH8 | RANGE_CH7 | ||||||
R/W-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RANGE_CH6 | RANGE_CH5 | ||||||
R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | RANGE_CH8 | R/W | 0h | Select the analog input voltage range. 0 : ±5V 1 : ±3.5V 2 : ±2.5V 3 : ±7V 4 : ±10V 5 : ±12V |
11-8 | RANGE_CH7 | R/W | 0h | |
7-4 | RANGE_CH6 | R/W | 0h | |
3-0 | RANGE_CH5 | R/W | 0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CM_RNG_CH[8:5] | ||||||
R/W-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CM_RNG_CH[4:1] | RESERVED | CM_EN_CH[8:5] | CM_EN_CH[4:1] | RESERVED | PD_CHIP | ||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-10 | RESERVED | R/W | 0h | Reserved. Do not change from the default reset value. |
9-8 | CM_RNG_CH[8:5] | R/W | 0h | CM_RNG_CH[4:1] sets the common-mode range for
channels 1, 2, 3, and 4. CM_RNG_CH[8:5] sets the common-mode range for channels 5, 6, 7, and 8. 0 : CM range is equal to ±RANGE / 2 1 : CM range is equal to ±6V 2 : CM range is equal to ±12V |
7-6 | CM_RNG_CH[4:1] | R/W | 0h | |
5-4 | RESERVED | R/W | 0h | Reserved. Do not change from the default reset value. |
3 | CM_EN_CH[8:5] | R/W | 0h | CM_EN_CH[4:1] enables wide common-mode range
control for channels 1 to 4. CM_EN_CH[8:5] enables the wide common-mode range control for channels 5 to 8. 0 : Wide common-mode range control disabled 1 : Wide common-mode range control enabled |
2 | CM_EN_CH[4:1] | R/W | 0h | |
1 | RESERVED | R/W | 0h | Reserved. Do not change from the default reset value. |
0 | PD_CHIP | R/W | 0h | Full chip power-down
control. 0 : Normal device operation 1 : Full device powered-down |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CM_CTRL_EN | RESERVED | |||||
R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-5 | RESERVED | R/W | 0h | Reserved. Do not change from the default reset value. |
4 | CM_CTRL_EN | R/W | 0h | Enable the wide common-mode range control for
all analog input channels. 0 : CM range for all analog input channels is ±12V 1 : CM range is user-defined in the CM_EN_CH[4:1], CM_EN_CH[8:5], CM_RNG_CH[4:1], and CM_RNG_CH[8:5] registers |
3-0 | RESERVED | R/W | 0h | Reserved. Do not change from the default reset value. |