JAJSSD2A October   2023  – December 2023 BQ25638

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 概要 (続き)
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power-On-Reset (POR)
      2. 7.3.2  Device Power Up from Battery
      3. 7.3.3  Device Power Up from Input Source
        1. 7.3.3.1 REGN LDO Power Up
        2. 7.3.3.2 Poor Source Qualification
        3. 7.3.3.3 Input Voltage Limit Threshold Setting (VINDPM Threshold)
        4. 7.3.3.4 Converter Power-Up
        5. 7.3.3.5 Input Current Optimizer (ICO)
        6. 7.3.3.6 Switching Frequency and Dithering Feature
      4. 7.3.4  Power Path Management
        1. 7.3.4.1 Narrow VDC Architecture
        2. 7.3.4.2 Dynamic Power Management
          1. 7.3.4.2.1 Input Current Limit on ILIM Pin
        3. 7.3.4.3 High Impedance (HIZ) Mode
      5. 7.3.5  Battery Charging Management
        1. 7.3.5.1 Autonomous Charging Cycle
        2. 7.3.5.2 Battery Charging Profile
        3. 7.3.5.3 Charging Termination
        4. 7.3.5.4 Thermistor Qualification
          1. 7.3.5.4.1 Advanced Temperature Profile in Charge Mode
          2. 7.3.5.4.2 TS Pin Thermistor Configuration
          3. 7.3.5.4.3 Cold/Hot Temperature Window in OTG Mode
          4. 7.3.5.4.4 JEITA Charge Rate Scaling
          5. 7.3.5.4.5 TS_BIAS Pin
        5. 7.3.5.5 Charging Safety Timers
      6. 7.3.6  USB On-The-Go (OTG)
        1. 7.3.6.1 Boost OTG Mode
      7. 7.3.7  Integrated 12-bit ADC for Monitoring
      8. 7.3.8  Status Outputs (INT , PG , STAT)
        1. 7.3.8.1 PG Pin Power Good Indicator
        2. 7.3.8.2 Charging Status Indicator (STAT)
        3. 7.3.8.3 Interrupt to Host (INT)
      9. 7.3.9  BATFET Control
        1. 7.3.9.1 Shutdown Mode
        2. 7.3.9.2 Ultra-Low Power Mode
        3. 7.3.9.3 System Power Reset
      10. 7.3.10 Protections
        1. 7.3.10.1 Voltage and Current Monitoring in Battery Only and HIZ Modes
          1. 7.3.10.1.1 Battery Overcurrent Protection
          2. 7.3.10.1.2 Battery Undervoltage Lockout
        2. 7.3.10.2 Voltage and Current Monitoring in Forward Mode
          1. 7.3.10.2.1 Input Overvoltage
          2. 7.3.10.2.2 System Overvoltage Protection (SYSOVP)
          3. 7.3.10.2.3 Forward Converter Cycle-by-Cycle Current Limit
          4. 7.3.10.2.4 System Short
          5. 7.3.10.2.5 Battery Overvoltage Protection (BATOVP)
          6. 7.3.10.2.6 Sleep and Poor Source Comparators
        3. 7.3.10.3 Voltage and Current Monitoring in Reverse Mode
          1. 7.3.10.3.1 Boost Mode Overvoltage Protection
          2. 7.3.10.3.2 Boost Mode Duty Cycle Protection
          3. 7.3.10.3.3 Boost Mode PMID Undervoltage Protection
          4. 7.3.10.3.4 Boost Mode Battery Undervoltage
          5. 7.3.10.3.5 Boost Converter Cycle-by-Cycle Current Limit
          6. 7.3.10.3.6 Boost Mode SYS Short
        4. 7.3.10.4 Thermal Regulation and Thermal Shutdown
          1. 7.3.10.4.1 Thermal Protection in Buck Mode
          2. 7.3.10.4.2 Thermal Protection in Boost Mode
          3. 7.3.10.4.3 Thermal Protection in Battery-only Mode
    4. 7.4 Device Functional Modes
      1. 7.4.1 Host Mode and Default Mode
      2. 7.4.2 Register Bit Reset
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
        1. 7.5.1.1 Data Validity
        2. 7.5.1.2 START and STOP Conditions
        3. 7.5.1.3 Byte Format
        4. 7.5.1.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 7.5.1.5 Target Address and Data Direction Bit
        6. 7.5.1.6 Single Write and Read
        7. 7.5.1.7 Multi-Write and Multi-Read
    6. 7.6 BQ25638 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Inductor Selection
        2. 8.2.2.2 Input Capacitor
        3. 8.2.2.3 Output Capacitor
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 サード・パーティ製品に関する免責事項
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

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7.6 BQ25638 Registers

Table 7-6 lists the memory-mapped registers for the BQ25638 registers. All register offset addresses not listed in Table 7-6 should be considered as reserved locations and the register contents should not be modified.

Table 7-6 BQ25638 Registers
AddressAcronymRegister NameSection
0x2REG0x02_Charge_Current_LimitCharge Current LimitGo
0x4REG0x04_Charge_Voltage_LimitCharge Voltage LimitGo
0x6REG0x06_Input_Current_LimitInput Current LimitGo
0x8REG0x08_Input_Voltage_LimitInput Voltage LimitGo
0xAREG0x0A_IOTG_regulationIOTG regulationGo
0xCREG0x0C_VOTG_regulationVOTG regulationGo
0xEREG0x0E_Minimal_System_VoltageMinimal System VoltageGo
0x10REG0x10_Precharge_ControlPrecharge ControlGo
0x12REG0x12_Termination_ControlTermination ControlGo
0x14REG0x14_Charge_Timer_ControlCharge Timer ControlGo
0x15REG0x15_Charger_Control_0Charger Control 0Go
0x16REG0x16_Charger_Control_1Charger Control 1Go
0x17REG0x17_Charger_Control_2Charger Control 2Go
0x18REG0x18_Charger_Control_3Charger Control 3Go
0x19REG0x19_Charger_Control_4Charger Control 4Go
0x1AREG0x1A_Charger_Control_5Charger Control 5Go
0x1CREG0x1C_NTC_Control_0NTC Control 0Go
0x1DREG0x1D_NTC_Control_1NTC Control 1Go
0x1EREG0x1E_NTC_Control_2NTC Control 2Go
0x1FREG0x1F_NTC_Control_3NTC Control 3Go
0x20REG0x20_Charger_Status_0Charger Status 0Go
0x21REG0x21_Charger_Status_1Charger Status 1Go
0x22REG0x22_FAULT_StatusFAULT StatusGo
0x23REG0x23_Charger_Flag_0Charger Flag 0Go
0x24REG0x24_Charger_Flag_1Charger Flag 1Go
0x25REG0x25_FAULT_FlagFAULT FlagGo
0x26REG0x26_Charger_Mask_0Charger Mask 0Go
0x27REG0x27_Charger_Mask_1Charger Mask 1Go
0x28REG0x28_FAULT_MaskFAULT MaskGo
0x29REG0x29_ICO_Current_LimitICO Current LimitGo
0x2BREG0x2B_ADC_ControlADC ControlGo
0x2CREG0x2C_ADC_Channel_DisableADC Channel DisableGo
0x2DREG0x2D_IBUS_ADCIBUS ADCGo
0x2FREG0x2F_IBAT_ADCIBAT ADCGo
0x31REG0x31_VBUS_ADCVBUS ADCGo
0x33REG0x33_VPMID_ADCVPMID ADCGo
0x35REG0x35_VBAT_ADCVBAT ADCGo
0x37REG0x37_VSYS_ADCVSYS ADCGo
0x39REG0x39_TS_ADCTS ADCGo
0x3BREG0x3B_TDIE_ADCTDIE ADCGo
0x3DREG0x3D_ADCIN_ADCADCIN ADCGo
0x3FREG0x3F_Part_InformationPart InformationGo
0x80REG0x80_Virtual_Control_0Virtual Control 0Go
0x81REG0x81_Virtual_Control_1Virtual Control 1Go

Complex bit access types are encoded to fit into small table cells. Table 7-7 shows the codes that are used for access types in this section.

Table 7-7 BQ25638 Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

7.6.1 REG0x02_Charge_Current_Limit Register (Address = 0x2) [Reset = 0x0640]

REG0x02_Charge_Current_Limit is shown in Figure 7-17 and described in Table 7-8.

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Figure 7-17 REG0x02_Charge_Current_Limit Register
15141312111098
RESERVEDICHG
R-0x0R/W-0x19
76543210
ICHGRESERVED
R/W-0x19R-0x0
Table 7-8 REG0x02_Charge_Current_Limit Register Field Descriptions
BitFieldTypeResetNotesDescription
15:12RESERVEDR0x0 Reserved
11:6ICHGR/W0x19This 16-bit register follows the little-endian convention.
Watchdog Timer expiration sets ICHG to 1/2 its previous value (rounded down)
Reset by:
REG_RESET
WATCHDOG		 Charge Current Regulation Limit:
NOTE: When Q4_FULLON=1, this register has a minimum value of 320mA POR: 2000mA (19h)
Range: 80mA-5040mA (1h-3Fh)
Clamped Low
Bit Step: 80mA
5:0RESERVEDR0x0 Reserved

7.6.2 REG0x04_Charge_Voltage_Limit Register (Address = 0x4) [Reset = 0x0D20]

REG0x04_Charge_Voltage_Limit is shown in Figure 7-18 and described in Table 7-9.

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Figure 7-18 REG0x04_Charge_Voltage_Limit Register
15141312111098
RESERVEDVREG
R-0x0R/W-0x1A4
76543210
VREGRESERVED
R/W-0x1A4R-0x0
Table 7-9 REG0x04_Charge_Voltage_Limit Register Field Descriptions
BitFieldTypeResetNotesDescription
15:12RESERVEDR0x0 Reserved
11:3VREGR/W0x1A4This 16-bit register follows the little-endian convention
Reset by:
REG_RESET		 Battery Voltage Regulation Limit: POR: 4200mV (1A4h)
Range: 3500mV-4800mV (15Eh-1E0h)
Clamped Low
Clamped High
Bit Step: 10mV
2:0RESERVEDR0x0 Reserved

7.6.3 REG0x06_Input_Current_Limit Register (Address = 0x6) [Reset = 0x0A00]

REG0x06_Input_Current_Limit is shown in Figure 7-19 and described in Table 7-10.

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Figure 7-19 REG0x06_Input_Current_Limit Register
15141312111098
RESERVEDIINDPM
R-0x0R/W-0xA0
76543210
IINDPMRESERVED
R/W-0xA0R-0x0
Table 7-10 REG0x06_Input_Current_Limit Register Field Descriptions
BitFieldTypeResetNotesDescription
15:12RESERVEDR0x0 Reserved
11:4IINDPMR/W0xA0This 16-bit register follows the little-endian convention
Reset by:
REG_RESET
Adapter Unplug		 Input Current Regulation Limit:
POR: 3200mA (A0h)
Range: 100mA-3200mA (5h-A0h)
Clamped Low
Clamped High
Bit Step: 20mA
3:0RESERVEDR0x0 Reserved

7.6.4 REG0x08_Input_Voltage_Limit Register (Address = 0x8) [Reset = 0x0DC0]

REG0x08_Input_Voltage_Limit is shown in Figure 7-20 and described in Table 7-11.

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Figure 7-20 REG0x08_Input_Voltage_Limit Register
15141312111098
RESERVEDVINDPM
R-0x0R/W-0x6E
76543210
VINDPMRESERVED
R/W-0x6ER-0x0
Table 7-11 REG0x08_Input_Voltage_Limit Register Field Descriptions
BitFieldTypeResetNotesDescription
15:14RESERVEDR0x0 Reserved
13:5VINDPMR/W0x6EThis 16-bit register follows the little-endian convention Absolute Input Voltage Regulation Limit: POR: 4400mV (6Eh)
Range: 3800mV-16800mV (5Fh-1A4h)
Clamped Low
Clamped High
Bit Step: 40mV
4:0RESERVEDR0x0 Reserved

7.6.5 REG0x0A_IOTG_regulation Register (Address = 0xA) [Reset = 0x04B0]

REG0x0A_IOTG_regulation is shown in Figure 7-21 and described in Table 7-12.

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Figure 7-21 REG0x0A_IOTG_regulation Register
15141312111098
RESERVEDIOTG
R-0x0R/W-0x4B
76543210
IOTGRESERVED
R/W-0x4BR-0x0
Table 7-12 REG0x0A_IOTG_regulation Register Field Descriptions
BitFieldTypeResetNotesDescription
15:12RESERVEDR0x0 Reserved
11:4IOTGR/W0x4BThis 16-bit register follows the little-endian convention
Reset by:
REG_RESET
WATCHDOG		 OTG mode current regulation limit: POR: 1500mA (4Bh)
Range: 100mA-3200mA (5h-A0h)
Clamped Low
Clamped High
Bit Step: 20mA
3:0RESERVEDR0x0 Reserved

7.6.6 REG0x0C_VOTG_regulation Register (Address = 0xC) [Reset = 0x1000]

REG0x0C_VOTG_regulation is shown in Figure 7-22 and described in Table 7-13.

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Figure 7-22 REG0x0C_VOTG_regulation Register
15141312111098
RESERVEDVOTG
R-0x0R/W-0x40
76543210
VOTGRESERVED
R/W-0x40R-0x0
Table 7-13 REG0x0C_VOTG_regulation Register Field Descriptions
BitFieldTypeResetNotesDescription
15:13RESERVEDR0x0 Reserved
12:6VOTGR/W0x40This 16-bit register follows the little-endian convention
Reset by:
REG_RESET		 OTG mode regulation voltage: POR: 5120mV (40h)
Range: 3840mV-9600mV (30h-78h)
Clamped Low
Clamped High
Bit Step: 80mV
5:0RESERVEDR0x0 Reserved

7.6.7 REG0x0E_Minimal_System_Voltage Register (Address = 0xE) [Reset = 0x0B00]

REG0x0E_Minimal_System_Voltage is shown in Figure 7-23 and described in Table 7-14.

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Figure 7-23 REG0x0E_Minimal_System_Voltage Register
15141312111098
RESERVEDVSYSMIN
R-0x0R/W-0x2C
76543210
VSYSMINRESERVED
R/W-0x2CR-0x0
Table 7-14 REG0x0E_Minimal_System_Voltage Register Field Descriptions
BitFieldTypeResetNotesDescription
15:12RESERVEDR0x0 Reserved
11:6VSYSMINR/W0x2CThis 16-bit register follows the little-endian convention
Reset by:
REG_RESET		 Minimal System Voltage: POR: 3520mV (2Ch)
Range: 2560mV-3840mV (20h-30h)
Clamped Low
Clamped High
Bit Step: 80mV
5:0RESERVEDR0x0 Reserved

7.6.8 REG0x10_Precharge_Control Register (Address = 0x10) [Reset = 0x00A0]

REG0x10_Precharge_Control is shown in Figure 7-24 and described in Table 7-15.

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Figure 7-24 REG0x10_Precharge_Control Register
15141312111098
RESERVEDIPRECHG
R-0x0R/W-0xA
76543210
IPRECHGRESERVED
R/W-0xAR-0x0
Table 7-15 REG0x10_Precharge_Control Register Field Descriptions
BitFieldTypeResetNotesDescription
15:10RESERVEDR0x0 Reserved
9:4IPRECHGR/W0xAThis 16-bit register follows the little-endian convention
Reset by:
REG_RESET		 Pre-charge current regulation limit:
NOTE: When Q4_FULLON=1, this register has a minimum value of 320mA POR: 200mA (Ah)
Range: 40mA-1000mA (2h-32h)
Clamped Low
Clamped High
Bit Step: 20mA
3:0RESERVEDR0x0 Reserved

7.6.9 REG0x12_Termination_Control Register (Address = 0x12) [Reset = 0x00A0]

REG0x12_Termination_Control is shown in Figure 7-25 and described in Table 7-16.

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Figure 7-25 REG0x12_Termination_Control Register
15141312111098
RESERVEDITERM
R-0x0R/W-0x14
76543210
ITERMRESERVED
R/W-0x14R-0x0
Table 7-16 REG0x12_Termination_Control Register Field Descriptions
BitFieldTypeResetNotesDescription
15:10RESERVEDR0x0 Reserved
9:3ITERMR/W0x14Reset by:
REG_RESET		 Termination Current Threshold:
NOTE: When Q4_FULLON=1, this register has a minimum value of 240mA POR: 200mA (14h)
Range: 30mA-1000mA (3h-64h)
Clamped Low
Clamped High
Bit Step: 10mA
2:0RESERVEDR0x0 Reserved

7.6.10 REG0x14_Charge_Timer_Control Register (Address = 0x14) [Reset = 0x0C]

REG0x14_Charge_Timer_Control is shown in Figure 7-26 and described in Table 7-17.

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Figure 7-26 REG0x14_Charge_Timer_Control Register
76543210
DIS_STATRESERVEDRESERVEDRESERVEDEN_TMR2XEN_SAFETY_TMRSPRECHG_TMRCHG_TMR
R/W-0x0R-0x0R-0x0R-0x0R/W-0x1R/W-0x1R/W-0x0R/W-0x0
Table 7-17 REG0x14_Charge_Timer_Control Register Field Descriptions
BitFieldTypeResetNotesDescription
7DIS_STATR/W0x0Reset by:
REG_RESET		 Disable the /STAT pin output 0b = Enable (Default)
1b = Disable
6RESERVEDR0x0 Reserved
5RESERVEDR0x0 Reserved
4RESERVEDR0x0 Reserved
3EN_TMR2XR/W0x1Reset by:
REG_RESET		 2X charging timer control 0b = Trickle charge, pre-charge and fast charge timer not slowed by 2X during input DPM or thermal regulation.
1b = Trickle charge, pre-charge and fast charge timer slowed by 2X during input DPM or thermal regulation (default)
2EN_SAFETY_TMRSR/W0x1Reset by:
REG_RESET
WATCHDOG		 Enable fast charge, pre-charge and trickle charge
timers 0b = Disable
1b = Enable (default)
1PRECHG_TMRR/W0x0Reset by:
REG_RESET		 Pre-charge safety timer setting 0b = 2.3 hrs (default)
1b = 0.6 hrs
0CHG_TMRR/W0x0Reset by:
REG_RESET		 Fast charge safety timer setting 0b = 14 hrs (default)
1b = 27 hrs

7.6.11 REG0x15_Charger_Control_0 Register (Address = 0x15) [Reset = 0x26]

REG0x15_Charger_Control_0 is shown in Figure 7-27 and described in Table 7-18.

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Figure 7-27 REG0x15_Charger_Control_0 Register
76543210
Q1_FULLONQ4_FULLONITRICKLETOPOFF_TMREN_TERMVINDPM_BAT_TRACKVRECHG
R/W-0x0R/W-0x0R/W-0x1R/W-0x0R/W-0x1R/W-0x1R/W-0x0
Table 7-18 REG0x15_Charger_Control_0 Register Field Descriptions
BitFieldTypeResetNotesDescription
7Q1_FULLONR/W0x0 Forces RBFET (Q1) into low resistance state (15 mΩ) ,
regardless of IINDPM setting. 0b = RBFET RDSON determined by IINDPM setting
1b = RBFET RDSON is always 15 mOhm
6Q4_FULLONR/W0x0 Forces BATFET (Q4) into low resistance state (7
mΩ), regardless of ICHG setting. 0b = BATFET RDSON determined by charge current
1b = BATFET RDSON is always 7 mOhm
5ITRICKLER/W0x1When Q4_FULLON, this setting is forced to 80mA
Reset by:
REG_RESET		 Trickle charging current setting: 0b = 20mA
1b = 80mA
4:3TOPOFF_TMRR/W0x0Reset by:
REG_RESET		 Top-off timer control: 00b = Disabled (default)
01b = 17.5 mins
10b = 35 mins
11b = 52 mins
2EN_TERMR/W0x1Reset by:
REG_RESET
WATCHDOG		 Enable termination 0b = Disable
1b = Enable (default)
1VINDPM_BAT_TRACKR/W0x1Reset by:
REG_RESET		 Sets VINDPM to track BAT voltage. Actual VINDPM is higher of the VINDPM register value and VBAT + VINDPM_BAT_TRACK. 0b = Disable function (VINDPM set by register)
1b = VBAT + 350 mV (default)
0VRECHGR/W0x0Reset by:
REG_RESET		 Battery Recharge Threshold Offset (Below VREG) 0b = 100mV (default)
1b = 200mV

7.6.12 REG0x16_Charger_Control_1 Register (Address = 0x16) [Reset = 0xA1]

REG0x16_Charger_Control_1 is shown in Figure 7-28 and described in Table 7-19.

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Figure 7-28 REG0x16_Charger_Control_1 Register
76543210
EN_AUTO_IBAT_DSCHGFORCE_IBAT_DSCHGEN_CHGEN_HIZFORCE_PMID_DSCHGWD_RSTWATCHDOG
R/W-0x1R/W-0x0R/W-0x1R/W-0x0R/W-0x0R/W-0x0R/W-0x1
Table 7-19 REG0x16_Charger_Control_1 Register Field Descriptions
BitFieldTypeResetNotesDescription
7EN_AUTO_IBAT_DSCHGR/W0x1Reset by:
REG_RESET		 Enable the auto battery discharging during the battery OVP fault 0b = The charger will NOT apply a discharging current on BAT during battery OVP triggered
1b = The charger will apply a discharging current on BAT during battery OVP triggered (default)
6FORCE_IBAT_DSCHGR/W0x0Reset by:
REG_RESET
WATCHDOG		 Enable BAT pull down current source 0b = Disable
1b = Enable
5EN_CHGR/W0x1Reset by:
REG_RESET
WATCHDOG		 Charger enable configuration 0b = Charge Disable
1b = Charge Enable (default)
4EN_HIZR/W0x0Reset by:
REG_RESET
WATCHDOG
Adapter Plug In		 Enable HIZ mode.
This bit will be reset to 0, when the adapter is plugged in at VBUS. 0b = Disable (default)
1b = Enable
3FORCE_PMID_DSCHGR/W0x0Reset by:
REG_RESET
WATCHDOG		 Enable PMID pull down current source (~30mA) 0b = Disable
1b = Enable
2WD_RSTR/W0x0Reset by:
REG_RESET		 I2C watch dog timer reset 0b = Normal (default)
1b = Reset (this bit goes back to 0 after timer reset)
1:0WATCHDOGR/W0x1Reset by:
REG_RESET		 Watchdog timer setting 00b = Disable
01b = 40s (default)
10b = 80s
11b = 160s

7.6.13 REG0x17_Charger_Control_2 Register (Address = 0x17) [Reset = 0x4F]

REG0x17_Charger_Control_2 is shown in Figure 7-29 and described in Table 7-20.

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Figure 7-29 REG0x17_Charger_Control_2 Register
76543210
REG_RSTTREGEN_DITHERSET_CONV_STRNSET_BATFET_STRNVBUS_OVP
R/W-0x0R/W-0x1R/W-0x0R/W-0x3R/W-0x1R/W-0x1
Table 7-20 REG0x17_Charger_Control_2 Register Field Descriptions
BitFieldTypeResetNotesDescription
7REG_RSTR/W0x0 Reset registers to default values and reset timer
Value resets to 0 after reset completes. 0b = Not reset (default)
1b = Reset
6TREGR/W0x1Reset by:
REG_RESET		 Thermal regulation thresholds. 0b = 60°C
1b = 120°C
5:4EN_DITHERR/W0x0Reset by:
REG_RESET		 Frequency Dither configuration: 00b = Disable
01b = 1X
10b = 2X
11b = 3X
3:2SET_CONV_STRNR/W0x3Reset by:
REG_RESET		 Adjust the drive strength of the converter to adjust
efficiency versus EMI.
00b = reduce drive strength three steps
01b = reduce drive strength two steps
10b = reduce drive strength one step
11b = maximum drive strength (default)
1SET_BATFET_STRNR/W0x1Reset by:
REG_RESET		 Adjust the drive strength of the BATFET to control
speed of turn on and turn off.
0b = reduce drive strength
1b = maximum drive strength (default)
0VBUS_OVPR/W0x1Reset by:
REG_RESET		 Set VBUS overvoltage protection threshold 0b = 6.3V
1b = 18.5V

7.6.14 REG0x18_Charger_Control_3 Register (Address = 0x18) [Reset = 0x04]

REG0x18_Charger_Control_3 is shown in Figure 7-30 and described in Table 7-21.

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Figure 7-30 REG0x18_Charger_Control_3 Register
76543210
RESERVEDEN_OTGDIS_PFM_OTGDIS_PFM_FWDBATFET_CTRL_WVBUSBATFET_DLYBATFET_CTRL
R-0x0R/W-0x0R/W-0x0R/W-0x0R/W-0x0R/W-0x1R/W-0x0
Table 7-21 REG0x18_Charger_Control_3 Register Field Descriptions
BitFieldTypeResetNotesDescription
7RESERVEDR0x0 Reserved
6EN_OTGR/W0x0Reset by:
REG_RESET
WATCHDOG		 OTG mode control 0b = OTG Disable (default)
1b = OTG Enable
5DIS_PFM_OTGR/W0x0Reset by:
REG_RESET		 Disable PFM in OTG boost mode 0b = Enable (Default)
1b = Disable
4DIS_PFM_FWDR/W0x0Reset by:
REG_RESET		 Disable PFM in forward buck mode 0b = Enable (Default)
1b = Disable
3BATFET_CTRL_WVBUSR/W0x0 Start system power reset with or without adapter present. 0b = Start system power reset after adapter is removed from VBUS. (default)
1b = Start system power reset whether or not adapter is present on VBUS.
2BATFET_DLYR/W0x1Reset by:
REG_RESET		 Delay time added to the taking action in bits [1:0] of the BATFET_CTRL 0b = Add 24ms delay
1b = Add 12s delay
1:0BATFET_CTRLR/W0x0Reset by:
REG_RESET		 BATFET control
The control logic of the BATFET to force the device enter different modes. 00b = Idle
01b = Shutdown Mode
10b = Ultra-Low Power Mode
11b = System Power Reset

7.6.15 REG0x19_Charger_Control_4 Register (Address = 0x19) [Reset = 0x85]

REG0x19_Charger_Control_4 is shown in Figure 7-31 and described in Table 7-22.

Return to the Summary Table.

Figure 7-31 REG0x19_Charger_Control_4 Register
76543210
IBAT_PKVBAT_UVLOVBAT_OTG_MINRESERVEDEN_EXT_ILIMFORCE_ICOEN_ICO
R/W-0x2R/W-0x0R/W-0x0R-0x0R/W-0x1R/W-0x0R/W-0x1
Table 7-22 REG0x19_Charger_Control_4 Register Field Descriptions
BitFieldTypeResetNotesDescription
7:6IBAT_PKR/W0x2Reset by:
REG_RESET		 Battery discharging over current protection threshold
setting 00b = 3A
01b = 6A
10b = 9A
11b = Reserved
5VBAT_UVLOR/W0x0Reset by:
REG_RESET		 Select the VBAT UVLO falling thresholds 0b = 2.2V (default)
1b = 1.8V
4VBAT_OTG_MINR/W0x0Reset by:
REG_RESET		 Select the minimal battery voltage to start the OTG mode 0b = 3V rising / 2.8 falling (default)
1b = 2.4V rising / 2.2 falling
3RESERVEDR0x0 Reserved
2EN_EXT_ILIMR/W0x1Reset by:
REG_RESET
WATCHDOG		 Enable External ILIM pin input current regulation 0b = Disable
1b = Enable
1FORCE_ICOR/W0x0Reset by:
REG_RESET
WATCHDOG		 Force Start Input Current Optimizer (ICO):
Note: This bit can only be set and always returns to 0 after ICO starts. This bit is only valid when EN_ICO = 1 0b = Do not force ICO
1b = Force ICO start
0EN_ICOR/W0x1Reset by:
REG_RESET		 Input Current Optimization (ICO) Algorithm Control: 0b = Disable ICO
1b = Enable ICO

7.6.16 REG0x1A_Charger_Control_5 Register (Address = 0x1A) [Reset = 0x00]

REG0x1A_Charger_Control_5 is shown in Figure 7-32 and described in Table 7-23.

Return to the Summary Table.

Figure 7-32 REG0x1A_Charger_Control_5 Register
76543210
PG_THTQON_RSTTSM_EXITFORCE_ISYS_DSCHGBATLOWV
R/W-0x0R/W-0x0R/W-0x0R/W-0x0R/W-0x0
Table 7-23 REG0x1A_Charger_Control_5 Register Field Descriptions
BitFieldTypeResetNotesDescription
7:5PG_THR/W0x0Reset by:
REG_RESET		 Programmable PG indicator falling threshold: 000b = 3.7V
001b = 7.4V
010b = 8V
011b = 10.4V
100b = 11V
101b = 13.4V
110b = 14V
111b = Reserved
4TQON_RSTR/W0x0 System Reset (tQON_RST) control: 0b = 11s
1b = 21s
3TSM_EXITR/W0x0 Ultra-Low Power Mode exit (tSM_EXIT) control: 0b = 700ms
1b = 10.5s
2FORCE_ISYS_DSCHGR/W0x0Reset by:
REG_RESET
WATCHDOG		 Enable SYS pull down current source 0b = Disable
1b = Enable
1:0BATLOWVR/W0x0 Battery precharge to fast-charge threshold: 00b = 3.0V
01b = 2.8V
10b = 2.7V
11b = 2.5V

7.6.17 REG0x1C_NTC_Control_0 Register (Address = 0x1C) [Reset = 0x0F]

REG0x1C_NTC_Control_0 is shown in Figure 7-33 and described in Table 7-24.

Return to the Summary Table.

Figure 7-33 REG0x1C_NTC_Control_0 Register
76543210
TS_IGNORECHG_RATETS_TH_OTG_HOTTS_TH_OTG_COLDTS_TH1TS_TH6
R/W-0x0R/W-0x0R/W-0x1R/W-0x1R/W-0x1R/W-0x1
Table 7-24 REG0x1C_NTC_Control_0 Register Field Descriptions
BitFieldTypeResetNotesDescription
7TS_IGNORER/W0x0Reset by:
REG_RESET
WATCHDOG		 Ignore the TS feedback, the charger will consider the
TS is always good to allow charging and OTG modes,
TS_STAT always reports TS_NORMAL 0b = Not ignore
1b = Ignore
6:5CHG_RATER/W0x0Reset by:
REG_RESET		 The charge rate used when device is in fast-charge. Once device enters JEITA region where charge current is reduced, the resulting current is = (ICHG * foldback ratio)/CHG_RATE: 00b = 1C
01b = 2C
10b = 4C
11b = 6C
4:3TS_TH_OTG_HOTR/W0x1Reset by:
REG_RESET		 OTG Mode TS_HOT falling voltage threshold (as a
percentage of REGN) to transition from normal
operation into suspended OTG mode. 00b = 55°C
01b = 60°C
10b = 65°C
11b = Disable
2TS_TH_OTG_COLDR/W0x1Reset by:
REG_RESET		 OTG Mode TS_COLD rising voltage threshold (as a
percentage of REGN) to transition from normal
operation into suspended OTG mode. 0b = -10°C
1b = -20°C
1TS_TH1R/W0x1Reset by:
REG_RESET		 TS TH1 comparator falling temperature
thresholds when a 103AT NTC thermistor is used,
RT1=5.24kΩ and RT2=30.31kΩ 0b = -5°C
1b = 0°C
0TS_TH6R/W0x1Reset by:
REG_RESET		 TS TH6 comparator rising temperature
thresholds when a 103AT NTC thermistor is used,
RT1=5.24kΩ and RT2=30.31kΩ 0b = 55°C
1b = 60°C

7.6.18 REG0x1D_NTC_Control_1 Register (Address = 0x1D) [Reset = 0x85]

REG0x1D_NTC_Control_1 is shown in Figure 7-34 and described in Table 7-25.

Return to the Summary Table.

Figure 7-34 REG0x1D_NTC_Control_1 Register
76543210
TS_TH2TS_TH3TS_TH4TS_TH5
R/W-0x2R/W-0x0R/W-0x1R/W-0x1
Table 7-25 REG0x1D_NTC_Control_1 Register Field Descriptions
BitFieldTypeResetNotesDescription
7:6TS_TH2R/W0x2Reset by:
REG_RESET		 TS TH2 comparator falling temperature
thresholds when a 103AT NTC thermistor is used,
RT1=5.24kΩ and RT2=30.31kΩ 00b = 5°C
01b = 7.5°C
10b = 10°C
11b = 12.5°C
5:4TS_TH3R/W0x0Reset by:
REG_RESET		 TS TH3 comparator falling temperature
thresholds when a 103AT NTC thermistor is used,
RT1=5.24kΩ and RT2=30.31kΩ 00b = 15°C
01b = 17.5°C
10b = 20°C
11b = 22.5°C
3:2TS_TH4R/W0x1Reset by:
REG_RESET		 TS TH4 comparator rising temperature
thresholds when a 103AT NTC thermistor is used,
RT1=5.24kΩ and RT2=30.31kΩ 00b = 32.5°C
01b = 35°C
10b = 37.5°C
11b = 40°C
1:0TS_TH5R/W0x1Reset by:
REG_RESET		 TS TH5 comparator rising temperature
thresholds when a 103AT NTC thermistor is used,
RT1=5.24kΩ and RT2=30.31kΩ 00b = 42.5°C
01b = 45°C
10b = 47.5°C
11b = 50°C

7.6.19 REG0x1E_NTC_Control_2 Register (Address = 0x1E) [Reset = 0x7F]

REG0x1E_NTC_Control_2 is shown in Figure 7-35 and described in Table 7-26.

Return to the Summary Table.

Figure 7-35 REG0x1E_NTC_Control_2 Register
76543210
TS_VSET_WARMTS_ISET_WARMTS_VSET_PREWARMTS_ISET_PREWARM
R/W-0x1R/W-0x3R/W-0x3R/W-0x3
Table 7-26 REG0x1E_NTC_Control_2 Register Field Descriptions
BitFieldTypeResetNotesDescription
7:6TS_VSET_WARMR/W0x1Reset by:
REG_RESET		 TS_WARM (TH5 - TH6) Voltage Setting 00b = Set VREG to VREG-300mV
01b = Set VREG to VREG-200mV
10b = Set VREG to VREG-100mV
11b = VREG unchanged
5:4TS_ISET_WARMR/W0x3Reset by:
REG_RESET		 TS_WARM (TH5 - TH6) Current Setting 00b = Charge Suspend
01b = Set ICHG to 20%
10b = Set ICHG to 40%
11b = ICHG unchanged
3:2TS_VSET_PREWARMR/W0x3Reset by:
REG_RESET		 TS_PREWARM (TH4 - TH5) Voltage Setting 00b = Set VREG to VREG-300mV
01b = Set VREG to VREG-200mV
10b = Set VREG to VREG-100mV
11b = VREG unchanged
1:0TS_ISET_PREWARMR/W0x3Reset by:
REG_RESET		 TS_PREWARM (TH4 - TH5) Current Setting 00b = Charge Suspend
01b = Set ICHG to 20%
10b = Set ICHG to 40%
11b = ICHG unchanged

7.6.20 REG0x1F_NTC_Control_3 Register (Address = 0x1F) [Reset = 0xDF]

REG0x1F_NTC_Control_3 is shown in Figure 7-36 and described in Table 7-27.

Return to the Summary Table.

Figure 7-36 REG0x1F_NTC_Control_3 Register
76543210
TS_VSET_COOLTS_ISET_COOLTS_VSET_PRECOOLTS_ISET_PRECOOL
R/W-0x3R/W-0x1R/W-0x3R/W-0x3
Table 7-27 REG0x1F_NTC_Control_3 Register Field Descriptions
BitFieldTypeResetNotesDescription
7:6TS_VSET_COOLR/W0x3Reset by:
REG_RESET		 TS_COOL (TH1 - TH2) Voltage Setting 00b = Set VREG to VREG-300mV
01b = Set VREG to VREG-200mV
10b = Set VREG to VREG-100mV
11b = VREG unchanged
5:4TS_ISET_COOLR/W0x1Reset by:
REG_RESET		 TS_COOL (TH1 - TH2) Current Setting 00b = Charge Suspend
01b = Set ICHG to 20%
10b = Set ICHG to 40%
11b = ICHG unchanged
3:2TS_VSET_PRECOOLR/W0x3Reset by:
REG_RESET		 TS_PRECOOL (TH2 - TH3) Voltage Setting: 00b = Set VREG to VREG-300mV
01b = Set VREG to VREG-200mV
10b = Set VREG to VREG-100mV
11b = VREG unchanged
1:0TS_ISET_PRECOOLR/W0x3Reset by:
REG_RESET		 TS_PRECOOL (TH2 - TH3) Current Setting: 00b = Charge Suspend
01b = Set ICHG to 20%
10b = Set ICHG to 40%
11b = ICHG unchanged

7.6.21 REG0x20_Charger_Status_0 Register (Address = 0x20) [Reset = 0x00]

REG0x20_Charger_Status_0 is shown in Figure 7-37 and described in Table 7-28.

Return to the Summary Table.

Figure 7-37 REG0x20_Charger_Status_0 Register
76543210
PG_STATADC_DONE_STATTREG_STATVSYS_STATIINDPM_STATVINDPM_STATSAFETY_TMR_STATWD_STAT
R-0x0R-0x0R-0x0R-0x0R-0x0R-0x0R-0x0R-0x0
Table 7-28 REG0x20_Charger_Status_0 Register Field Descriptions
BitFieldTypeResetDescription
7PG_STATR0x0 Power Good Indicator Status: 0b = VBUS below PG_TH
1b = VBUS above PG_TH
6ADC_DONE_STATR0x0 ADC Conversion Status (in one-shot mode only)
Note: Always reads 0 in continuous mode 0b = Conversion not complete
1b = Conversion complete
5TREG_STATR0x0 IC Thermal regulation status 0b = Normal
1b = Device in thermal regulation
4VSYS_STATR0x0 VSYS Regulation Status (forward mode) 0b = Not in VSYSMIN regulation (BAT>VSYSMIN)
1b = In VSYSMIN regulation (BAT<VSYSMIN)
3IINDPM_STATR0x0 IINDPM status (forward mode) or IOTG status (OTG mode) 0b = Normal
1b = In IINDPM regulation or IOTG regulation
2VINDPM_STATR0x0 VINDPM status (forward mode) or VOTG status (OTG mode, backup mode) 0b = Normal
1b = In VINDPM regulation or VOTG regualtion
1SAFETY_TMR_STATR0x0 Fast charge, trickle charge and pre-charge timer status 0b = Normal
1b = Safety timer expired
0WD_STATR0x0 I2C watch dog timer status 0b = Normal
1b = WD timer expired

7.6.22 REG0x21_Charger_Status_1 Register (Address = 0x21) [Reset = 0x00]

REG0x21_Charger_Status_1 is shown in Figure 7-38 and described in Table 7-29.

Return to the Summary Table.

Figure 7-38 REG0x21_Charger_Status_1 Register
76543210
ICO_STATCHG_STATVBUS_STAT
R-0x0R-0x0R-0x0
Table 7-29 REG0x21_Charger_Status_1 Register Field Descriptions
BitFieldTypeResetDescription
7:6ICO_STATR0x0 Input Current Optimizer (ICO) Status: 00b = ICO Disabled
01b = ICO Optimization in Progress
10b = Maximum input current detected
11b = ICO Routine Suspended
5:3CHG_STATR0x0 Charge Status: 000b = Not Charging
001b = Trickle Charge
010b = Pre-charge
011b = Fast Charge (CC)
100b = Taper Charge (CV)
101b = Reserved
110b = Top-off Timer Active Charging
111b = Charge Termination Done
2:0VBUS_STATR0x0 VBUS status: 000b = Not powered from VBUS
100b = Unknown adaptor (IINDPM Default)
111b = In boost OTG

7.6.23 REG0x22_FAULT_Status Register (Address = 0x22) [Reset = 0x00]

REG0x22_FAULT_Status is shown in Figure 7-39 and described in Table 7-30.

Return to the Summary Table.

Figure 7-39 REG0x22_FAULT_Status Register
76543210
VBUS_FAULT_STATBAT_FAULT_STATVSYS_FAULT_STATOTG_FAULT_STATTSHUT_STATTS_STAT
R-0x0R-0x0R-0x0R-0x0R-0x0R-0x0
Table 7-30 REG0x22_FAULT_Status Register Field Descriptions
BitFieldTypeResetDescription
7VBUS_FAULT_STATR0x0 VBUS over-voltage status 0b = Normal
1b = Device in over voltage protection
6BAT_FAULT_STATR0x0 Battery fault status 0b = Normal
1b = Dead or over-voltage battery detected
5VSYS_FAULT_STATR0x0 VSYS under voltage and over voltage status 0b = Normal
1b = SYS in SYS short circuit or over voltage
4OTG_FAULT_STATR0x0 OTG under voltage and over voltage status. 0b = Normal
1b = Fault Detected
3TSHUT_STATR0x0 IC temperature shutdown status 0b = Normal
1b = Device in thermal shutdown protection
2:0TS_STATR0x0 The TS temperature zone. 000b = TS_NORMAL
001b = TS_COLD or TS_OTG_COLD
010b = TS_HOT or TS_OTG_HOT
011b = TS_COOL
100b = TS_WARM
101b = TS_PRECOOL
110b = TS_PREWARM
111b = RESERVED

7.6.24 REG0x23_Charger_Flag_0 Register (Address = 0x23) [Reset = 0x00]

REG0x23_Charger_Flag_0 is shown in Figure 7-40 and described in Table 7-31.

Return to the Summary Table.

Figure 7-40 REG0x23_Charger_Flag_0 Register
76543210
PG_FLAGADC_DONE_FLAGTREG_FLAGVSYS_FLAGIINDPM_FLAGVINDPM_FLAGSAFETY_TMR_FLAGWD_FLAG
R-0x0R-0x0R-0x0R-0x0R-0x0R-0x0R-0x0R-0x0
Table 7-31 REG0x23_Charger_Flag_0 Register Field Descriptions
BitFieldTypeResetDescription
7PG_FLAGR0x0 Power Good indicator flag: Access: R (ClearOnRead)
0b = Normal
1b = PG status changed
6ADC_DONE_FLAGR0x0 ADC convertersion flag (only in one-shot mode) Access: R (ClearOnRead)
0b = Conversion not completed
1b = Conversion completed
5TREG_FLAGR0x0 IC Thermal regulation flag Access: R (ClearOnRead)
0b = Normal
1b = TREG signal rising threshold detected
4VSYS_FLAGR0x0 VSYS min regulation flag Access: R (ClearOnRead)
0b = Normal
1b = Entered or exited VSYS min regulation
3IINDPM_FLAGR0x0 IINDPM or IOTG flag Access: R (ClearOnRead)
0b = Normal
1b = IINDPM signal rising edge detected
2VINDPM_FLAGR0x0 VINDPM or VOTG flag Access: R (ClearOnRead)
0b = Normal
1b = VINDPM regulation signal rising edge detected
1SAFETY_TMR_FLAGR0x0 Fast charge, trickle charge and pre-charge timer flag Access: R (ClearOnRead)
0b = Normal
1b = Fast chargeg timer expired rising edge detected
0WD_FLAGR0x0 I2C watchdog timer flag Access: R (ClearOnRead)
0b = Normal
1b = WD timer signal rising edge detected

7.6.25 REG0x24_Charger_Flag_1 Register (Address = 0x24) [Reset = 0x00]

REG0x24_Charger_Flag_1 is shown in Figure 7-41 and described in Table 7-32.

Return to the Summary Table.

Figure 7-41 REG0x24_Charger_Flag_1 Register
76543210
RESERVEDICO_FLAGRESERVEDCHG_FLAGRESERVEDVBUS_FLAG
R-0x0R-0x0R-0x0R-0x0R-0x0R-0x0
Table 7-32 REG0x24_Charger_Flag_1 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6ICO_FLAGR0x0 Input Current Optimizer (ICO) flag Access: R (ClearOnRead)
0b = Normal
1b = ICO_STAT[1:0] changed (transition to any state)
5:4RESERVEDR0x0 Reserved
3CHG_FLAGR0x0 Charge status flag Access: R (ClearOnRead)
0b = Normal
1b = Charge status changed
2:1RESERVEDR0x0 Reserved
0VBUS_FLAGR0x0 VBUS status flag Access: R (ClearOnRead)
0b = Normal
1b = VBUS status changed

7.6.26 REG0x25_FAULT_Flag Register (Address = 0x25) [Reset = 0x00]

REG0x25_FAULT_Flag is shown in Figure 7-42 and described in Table 7-33.

Return to the Summary Table.

Figure 7-42 REG0x25_FAULT_Flag Register
76543210
VBUS_FAULT_FLAGBAT_FAULT_FLAGVSYS_FAULT_FLAGOTG_FAULT_FLAGTSHUT_FLAGRESERVEDTS_FLAG
R-0x0R-0x0R-0x0R-0x0R-0x0R-0x0R-0x0
Table 7-33 REG0x25_FAULT_Flag Register Field Descriptions
BitFieldTypeResetDescription
7VBUS_FAULT_FLAGR0x0 VBUS over-voltage flag Access: R (ClearOnRead)
0b = Normal
1b = Entered VBUS OVP
6BAT_FAULT_FLAGR0x0 VBAT over-voltage flag Access: R (ClearOnRead)
0b = Normal
1b = Entered VBAT OVP
5VSYS_FAULT_FLAGR0x0 VSYS over voltage and SYS short flag Access: R (ClearOnRead)
0b = Normal
1b = Stopped switching due to system over-voltage or SYS short fault
4OTG_FAULT_FLAGR0x0 OTG under voltage and over voltage flag Access: R (ClearOnRead)
0b = Normal
1b = Stopped OTG due to VBUS under voltage or over voltage fault
3TSHUT_FLAGR0x0 IC thermal shutdown flag Access: R (ClearOnRead)
0b = Normal
1b = TS shutdown signal rising threshold detected
2:1RESERVEDR0x0 Reserved
0TS_FLAGR0x0 TS status flag Access: R (ClearOnRead)
0b = Normal
1b = A change to TS status was detected

7.6.27 REG0x26_Charger_Mask_0 Register (Address = 0x26) [Reset = 0x00]

REG0x26_Charger_Mask_0 is shown in Figure 7-43 and described in Table 7-34.

Return to the Summary Table.

Figure 7-43 REG0x26_Charger_Mask_0 Register
76543210
PG_MASKADC_DONE_MASKTREG_MASKVSYS_MASKIINDPM_MASKVINDPM_MASKSAFETY_TMR_MASKWD_MASK
R/W-0x0R/W-0x0R/W-0x0R/W-0x0R/W-0x0R/W-0x0R/W-0x0R/W-0x0
Table 7-34 REG0x26_Charger_Mask_0 Register Field Descriptions
BitFieldTypeResetNotesDescription
7PG_MASKR/W0x0Reset by:
REG_RESET		 Power Good indicator INT mask 0b = PG status change does produce INT pulse
1b = PG status change does not produce INT pulse
6ADC_DONE_MASKR/W0x0Reset by:
REG_RESET		 ADC conversion INT mask (only in one-shot mode) 0b = ADC conversion done does produce INT pulse
1b = ADC conversion done does not produce INT pulse
5TREG_MASKR/W0x0Reset by:
REG_RESET		 IC thermal regulation INT mask 0b = Entering TREG does produce INT
1b = Entering TREG does not produce INT
4VSYS_MASKR/W0x0Reset by:
REG_RESET		 VSYS min regulation INT mask 0b = Enter or exit VSYSMIN regulation does produce INT pulse
1b = Enter or exit VSYSMIN regulation does not produce INT pulse
3IINDPM_MASKR/W0x0Reset by:
REG_RESET		 IINDPM or IOTG INT mask 0b = Enter IINDPM or IOTG does produce INT pulse
1b = Enter IINDPM or IOTG does not produce INT pulse
2VINDPM_MASKR/W0x0Reset by:
REG_RESET		 VINDPM or VOTG INT mask 0b = Enter VINDPM does produce INT pulse
1b = Enter VINDPM does not produce INT pulse
1SAFETY_TMR_MASKR/W0x0Reset by:
REG_RESET		 Fast charge, trickle charge and pre-charge timer INT mask 0b = Fast charge, trickle charge or pre-charge timer expiration does produce INT
1b = Fast charge, trickle charge or pre-charge timer expiration does not produce INT
0WD_MASKR/W0x0Reset by:
REG_RESET		 I2C watch dog timer INT mask 0b = I2C watch dog timer expired does produce INT pulse
1b = I2C watch dog timer expired does not produce INT pulse

7.6.28 REG0x27_Charger_Mask_1 Register (Address = 0x27) [Reset = 0x00]

REG0x27_Charger_Mask_1 is shown in Figure 7-44 and described in Table 7-35.

Return to the Summary Table.

Figure 7-44 REG0x27_Charger_Mask_1 Register
76543210
RESERVEDICO_MASKRESERVEDCHG_MASKRESERVEDVBUS_MASK
R-0x0R/W-0x0R-0x0R/W-0x0R-0x0R/W-0x0
Table 7-35 REG0x27_Charger_Mask_1 Register Field Descriptions
BitFieldTypeResetNotesDescription
7RESERVEDR0x0 Reserved
6ICO_MASKR/W0x0Reset by:
REG_RESET		 Input Current Optimizer (ICO) INT mask 0b = ICO_STAT change does produce INT
1b = ICO_STAT change does not produce INT
5:4RESERVEDR0x0 Reserved
3CHG_MASKR/W0x0Reset by:
REG_RESET		 Charge status INT mask 0b = Charging status change does produce INT
1b = Charging status change does not produce INT
2:1RESERVEDR0x0 Reserved
0VBUS_MASKR/W0x0Reset by:
REG_RESET		 VBUS status INT mask 0b = VBUS status change does produce INT
1b = VBUS status change does not produce INT

7.6.29 REG0x28_FAULT_Mask Register (Address = 0x28) [Reset = 0x00]

REG0x28_FAULT_Mask is shown in Figure 7-45 and described in Table 7-36.

Return to the Summary Table.

Figure 7-45 REG0x28_FAULT_Mask Register
76543210
VBUS_FAULT_MASKBAT_FAULT_MASKVSYS_FAULT_MASKOTG_FAULT_MASKTSHUT_MASKRESERVEDTS_MASK
R/W-0x0R/W-0x0R/W-0x0R/W-0x0R/W-0x0R-0x0R/W-0x0
Table 7-36 REG0x28_FAULT_Mask Register Field Descriptions
BitFieldTypeResetNotesDescription
7VBUS_FAULT_MASKR/W0x0Reset by:
REG_RESET		 VBUS over-voltage INT mask 0b = Entering VBUS OVP does produce INT
1b = Entering VBUS OVP does not produce INT
6BAT_FAULT_MASKR/W0x0Reset by:
REG_RESET		 IBAT/VBAT over-current/over-voltage INT mask 0b = Entering IBAT OCP or VBAT OVP does produce INT
1b = Entering IBAT OCP or VBAT OVP does not produce INT
5VSYS_FAULT_MASKR/W0x0Reset by:
REG_RESET		 VSYS over voltage and SYS short INT mask 0b = System over-voltage or SYS short fault does produce INT
1b = Neither system over voltage nor SYS short fault produces INT
4OTG_FAULT_MASKR/W0x0Reset by:
REG_RESET		 OTG under voltage and over voltage INT mask 0b = OTG VBUS under voltage or over voltage fault does produce INT
1b = Neither OTG VBUS under voltage nor over voltage fault produces INT
3TSHUT_MASKR/W0x0Reset by:
REG_RESET		 IC thermal shutdown INT mask 0b = TSHUT does produce INT
1b = TSHUT does not produce INT
2:1RESERVEDR0x0 Reserved
0TS_MASKR/W0x0Reset by:
REG_RESET		 Temperature charging profile INT mask 0b = A change to TS temperature zone does produce INT
1b = A change to the TS temperature zone does not produce INT

7.6.30 REG0x29_ICO_Current_Limit Register (Address = 0x29) [Reset = 0x0000]

REG0x29_ICO_Current_Limit is shown in Figure 7-46 and described in Table 7-37.

Return to the Summary Table.

Figure 7-46 REG0x29_ICO_Current_Limit Register
15141312111098
RESERVEDICO_IINDPM
R-0x0R-0x0
76543210
ICO_IINDPMRESERVED
R-0x0R-0x0
Table 7-37 REG0x29_ICO_Current_Limit Register Field Descriptions
BitFieldTypeResetNotesDescription
15:12RESERVEDR0x0 Reserved
11:4ICO_IINDPMR0x0This 16-bit register follows the little-endian convention
Reset by:
Adapter Unplug		 Optimized Input Current Limit when ICO is enabled: POR: 0mA (0h)
Range: 100mA-3200mA (5h-A0h)
Clamped Low
Clamped High
Bit Step: 20mA
3:0RESERVEDR0x0 Reserved

7.6.31 REG0x2B_ADC_Control Register (Address = 0x2B) [Reset = 0x30]

REG0x2B_ADC_Control is shown in Figure 7-47 and described in Table 7-38.

Return to the Summary Table.

Figure 7-47 REG0x2B_ADC_Control Register
76543210
EN_ADCADC_RATEADC_SAMPLEADC_AVGADC_AVG_INITRESERVEDDIS_ADCIN_ADC
R/W-0x0R/W-0x0R/W-0x3R/W-0x0R/W-0x0R-0x0R/W-0x0
Table 7-38 REG0x2B_ADC_Control Register Field Descriptions
BitFieldTypeResetNotesDescription
7EN_ADCR/W0x0Reset by:
REG_RESET
WATCHDOG		 ADC Control 0b = Disable (default)
1b = Enable
6ADC_RATER/W0x0Reset by:
REG_RESET		 ADC conversion rate control 0b = Continuous conversion (default)
1b = One shot conversion
5:4ADC_SAMPLER/W0x3Reset by:
REG_RESET		 ADC sample speed 00b = 11 bit effective resolution
01b = 10 bit effective resolution
10b = 9 bit effective resolution
11b = 8 bit effective resolution (default)
3ADC_AVGR/W0x0Reset by:
REG_RESET		 ADC average control 0b = Single value (default)
1b = Running average
2ADC_AVG_INITR/W0x0Reset by:
REG_RESET		 ADC acerage initial value control 0b = Start average using the existing register value
1b = Start average using a new ADC conversion
1RESERVEDR0x0 Reserved
0DIS_ADCIN_ADCR/W0x0Reset by:
REG_RESET		 ADCIN ADC channel disable 0b = Enable
1b = Disable

7.6.32 REG0x2C_ADC_Channel_Disable Register (Address = 0x2C) [Reset = 0x00]

REG0x2C_ADC_Channel_Disable is shown in Figure 7-48 and described in Table 7-39.

Return to the Summary Table.

Figure 7-48 REG0x2C_ADC_Channel_Disable Register
76543210
DIS_IBUS_ADCDIS_IBAT_ADCDIS_VBUS_ADCDIS_VBAT_ADCDIS_VSYS_ADCDIS_TS_ADCDIS_TDIE_ADCDIS_VPMID_ADC
R/W-0x0R/W-0x0R/W-0x0R/W-0x0R/W-0x0R/W-0x0R/W-0x0R/W-0x0
Table 7-39 REG0x2C_ADC_Channel_Disable Register Field Descriptions
BitFieldTypeResetNotesDescription
7DIS_IBUS_ADCR/W0x0Reset by:
REG_RESET		 IBUS ADC channel disable 0b = Enable
1b = Disable
6DIS_IBAT_ADCR/W0x0Reset by:
REG_RESET		 IBAT ADC control 0b = Enable
1b = Disable
5DIS_VBUS_ADCR/W0x0Reset by:
REG_RESET		 VBUS ADC control 0b = Enable
1b = Disable
4DIS_VBAT_ADCR/W0x0Reset by:
REG_RESET		 VBAT ADC control 0b = Enable
1b = Disable
3DIS_VSYS_ADCR/W0x0Reset by:
REG_RESET		 VSYS ADC control 0b = Enable
1b = Disable
2DIS_TS_ADCR/W0x0Reset by:
REG_RESET		 TS ADC control 0b = Enable
1b = Disable
1DIS_TDIE_ADCR/W0x0Reset by:
REG_RESET		 TDIE ADC control 0b = Enable
1b = Disable
0DIS_VPMID_ADCR/W0x0Reset by:
REG_RESET		 VPMID ADC control 0b = Enable
1b = Disable

7.6.33 REG0x2D_IBUS_ADC Register (Address = 0x2D) [Reset = 0x0000]

REG0x2D_IBUS_ADC is shown in Figure 7-49 and described in Table 7-40.

Return to the Summary Table.

Figure 7-49 REG0x2D_IBUS_ADC Register
15141312111098
IBUS_ADC
R-0x0
76543210
IBUS_ADCRESERVED
R-0x0R-0x0
Table 7-40 REG0x2D_IBUS_ADC Register Field Descriptions
BitFieldTypeResetDescription
15:1IBUS_ADCR0x0 IBUS ADC reading
Reported in 2 's Complement.
When the current is flowing from VBUS to PMID, IBUS ADC reports positive value, and when the current is flowing from PMID to VBUS, IBUS ADC reports negative value. POR: 0mA(0h)
Format: 2s Complement
Range: -5000mA - 5000mA (7830h-7D0h)
Clamped Low
Clamped High
Bit Step: 2.5mA
0RESERVEDR0x0 Reserved

7.6.34 REG0x2F_IBAT_ADC Register (Address = 0x2F) [Reset = 0x0000]

REG0x2F_IBAT_ADC is shown in Figure 7-50 and described in Table 7-41.

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Figure 7-50 REG0x2F_IBAT_ADC Register
15141312111098
IBAT_ADC
R-0x0
76543210
IBAT_ADCRESERVED
R-0x0R-0x0
Table 7-41 REG0x2F_IBAT_ADC Register Field Descriptions
BitFieldTypeResetDescription
15:3IBAT_ADCR0x0 IBAT ADC reading
Reported in 2 's Complement. The IBAT ADC reports positive value for the battery charging current,
and negative value for the battery discharging current. POR: 0mA (0h)
Format: 2s Complement
Range: -10000mA-5025mA (1830h-3EDh)
Clamped Low
Clamped High
Bit Step: 5mA
2:0RESERVEDR0x0 Reserved

7.6.35 REG0x31_VBUS_ADC Register (Address = 0x31) [Reset = 0x0000]

REG0x31_VBUS_ADC is shown in Figure 7-51 and described in Table 7-42.

Return to the Summary Table.

Figure 7-51 REG0x31_VBUS_ADC Register
15141312111098
RESERVEDVBUS_ADC
R-0x0R-0x0
76543210
VBUS_ADCRESERVED
R-0x0R-0x0
Table 7-42 REG0x31_VBUS_ADC Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR0x0 Reserved
14:2VBUS_ADCR0x0 VBUS ADC reading POR: 0mV (0h)
Range: 0mV-20000mV (0h-FA0h)
Clamped High
Bit Step: 5mV
1:0RESERVEDR0x0 Reserved

7.6.36 REG0x33_VPMID_ADC Register (Address = 0x33) [Reset = 0x0000]

REG0x33_VPMID_ADC is shown in Figure 7-52 and described in Table 7-43.

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Figure 7-52 REG0x33_VPMID_ADC Register
15141312111098
RESERVEDVPMID_ADC
R-0x0R-0x0
76543210
VPMID_ADCRESERVED
R-0x0R-0x0
Table 7-43 REG0x33_VPMID_ADC Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR0x0 Reserved
14:2VPMID_ADCR0x0 VPMID ADC reading POR: 0mV (0h)
Range: 0mV-20000mV (0h-FA0h)
Clamped High
Bit Step: 5mV
1:0RESERVEDR0x0 Reserved

7.6.37 REG0x35_VBAT_ADC Register (Address = 0x35) [Reset = 0x0000]

REG0x35_VBAT_ADC is shown in Figure 7-53 and described in Table 7-44.

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Figure 7-53 REG0x35_VBAT_ADC Register
15141312111098
RESERVEDVBAT_ADC
R-0x0R-0x0
76543210
VBAT_ADCRESERVED
R-0x0R-0x0
Table 7-44 REG0x35_VBAT_ADC Register Field Descriptions
BitFieldTypeResetDescription
15:13RESERVEDR0x0 Reserved
12:1VBAT_ADCR0x0 VBAT ADC reading POR: 0mV(0h)
Range: 0mV - 5000mV (0h-FA0h)
Clamped High
Bit Step: 1.25mV
0RESERVEDR0x0 Reserved

7.6.38 REG0x37_VSYS_ADC Register (Address = 0x37) [Reset = 0x0000]

REG0x37_VSYS_ADC is shown in Figure 7-54 and described in Table 7-45.

Return to the Summary Table.

Figure 7-54 REG0x37_VSYS_ADC Register
15141312111098
RESERVEDVSYS_ADC
R-0x0R-0x0
76543210
VSYS_ADCRESERVED
R-0x0R-0x0
Table 7-45 REG0x37_VSYS_ADC Register Field Descriptions
BitFieldTypeResetDescription
15:13RESERVEDR0x0 Reserved
12:1VSYS_ADCR0x0 VSYS ADC reading POR: 0mV(0h)
Range: 0mV - 5000mV (0h-FA0h)
Clamped High
Bit Step: 1.25mV
0RESERVEDR0x0 Reserved

7.6.39 REG0x39_TS_ADC Register (Address = 0x39) [Reset = 0x0000]

REG0x39_TS_ADC is shown in Figure 7-55 and described in Table 7-46.

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Figure 7-55 REG0x39_TS_ADC Register
15141312111098
RESERVEDTS_ADC
R-0x0R-0x0
76543210
TS_ADC
R-0x0
Table 7-46 REG0x39_TS_ADC Register Field Descriptions
BitFieldTypeResetDescription
15:12RESERVEDR0x0 Reserved
11:0TS_ADCR0x0 TS ADC reading POR: 0%(0h)
Range: 0% - 99.90234375% (0h-3FFh)
Clamped High
Bit Step: 0.09765625%

7.6.40 REG0x3B_TDIE_ADC Register (Address = 0x3B) [Reset = 0x0000]

REG0x3B_TDIE_ADC is shown in Figure 7-56 and described in Table 7-47.

Return to the Summary Table.

Figure 7-56 REG0x3B_TDIE_ADC Register
15141312111098
RESERVEDTDIE_ADC
R-0x0R-0x0
76543210
TDIE_ADC
R-0x0
Table 7-47 REG0x3B_TDIE_ADC Register Field Descriptions
BitFieldTypeResetDescription
15:12RESERVEDR0x0 Reserved
11:0TDIE_ADCR0x0 TDIE ADC reading
Reported in 2 's Complement. POR: 0°C(0h)
Format: 2s Complement
Range: -40°C - 150°C (FB0h-12Ch)
Clamped Low
Clamped High
Bit Step: 0.5°C

7.6.41 REG0x3D_ADCIN_ADC Register (Address = 0x3D) [Reset = 0x0000]

REG0x3D_ADCIN_ADC is shown in Figure 7-57 and described in Table 7-48.

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Figure 7-57 REG0x3D_ADCIN_ADC Register
15141312111098
RESERVEDADCIN_ADC
R-0x0R-0x0
76543210
ADCIN_ADC
R-0x0
Table 7-48 REG0x3D_ADCIN_ADC Register Field Descriptions
BitFieldTypeResetDescription
15:12RESERVEDR0x0 Reserved
11:0ADCIN_ADCR0x0 ADCIN ADC reading POR: 0mV(0h)
Range: 0mV - 1000mV (0h-FA0h)
Clamped High
Bit Step: 0.25mV

7.6.42 REG0x3F_Part_Information Register (Address = 0x3F) [Reset = 0x08]

REG0x3F_Part_Information is shown in Figure 7-58 and described in Table 7-49.

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Figure 7-58 REG0x3F_Part_Information Register
76543210
TEST_REVPNDEV_REV
R-0x0R-0x2R-0x0
Table 7-49 REG0x3F_Part_Information Register Field Descriptions
BitFieldTypeResetDescription
7:6TEST_REVR0x0 Test Revision
5:2PNR0x2 Device Part number
1:0DEV_REVR0x0 Device Revision

7.6.43 REG0x80_Virtual_Control_0 Register (Address = 0x80) [Reset = 0x11]

REG0x80_Virtual_Control_0 is shown in Figure 7-59 and described in Table 7-50.

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Figure 7-59 REG0x80_Virtual_Control_0 Register
76543210
REG_RSTRESERVEDRESERVEDEN_EXTILIMRESERVEDWD_RSTWATCHDOG
R/W-0x0R-0x0R-0x0R/W-0x1R-0x0R/W-0x0R/W-0x1
Table 7-50 REG0x80_Virtual_Control_0 Register Field Descriptions
BitFieldTypeResetNotesDescription
7REG_RSTR/W0x0 Reset registers to default values and reset timer
Value resets to 0 after reset completes. 0b = Not reset (default)
1b = Reset
6RESERVEDR0x0 Reserved
5RESERVEDR0x0 Reserved
4EN_EXTILIMR/W0x1Reset by:
REG_RESET		 Enable the external ILIM_HIZ pin input current regulation 0b = Disable
1b = Enable (default)
3RESERVEDR0x0 Reserved
2WD_RSTR/W0x0Reset by:
REG_RESET		 I2C watch dog timer reset 0b = Normal (default)
1b = Reset (this bit goes back to 0 after timer reset)
1:0WATCHDOGR/W0x1Reset by:
REG_RESET		 Watchdog timer setting 00b = Disable
01b = 40s (default)
10b = 80s
11b = 160s

7.6.44 REG0x81_Virtual_Control_1 Register (Address = 0x81) [Reset = 0x80]

REG0x81_Virtual_Control_1 is shown in Figure 7-60 and described in Table 7-51.

Return to the Summary Table.

Figure 7-60 REG0x81_Virtual_Control_1 Register
76543210
EN_CHGRESERVEDFORCE_PMID_DSCHGEN_OTG
R/W-0x1R-0x0R/W-0x0R/W-0x0
Table 7-51 REG0x81_Virtual_Control_1 Register Field Descriptions
BitFieldTypeResetNotesDescription
7EN_CHGR/W0x1Reset by:
REG_RESET
WATCHDOG		 Enable PMID pull down current source (~30mA) 0b = Charge Disable
1b = Charge Enable (default)
6:2RESERVEDR0x0 Reserved
1FORCE_PMID_DSCHGR/W0x0Reset by:
REG_RESET		 Enable PMID pull down current source (~30mA) 0b = Disable (default)
1b = Enable
0EN_OTGR/W0x0Reset by:
REG_RESET
WATCHDOG		 OTG mode control 0b = OTG Disable (default)
1b = OTG Enable