JAJSG82A November   2015  – September 2018

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      概略回路図
  4. 改訂履歴
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Charge Pump Control
      2. 7.3.2 Pin Enable Controls
        1. 7.3.2.1 External Control of CHG and DSG Output Drivers
        2. 7.3.2.2 External Control of PCHG Output Driver
        3. 7.3.2.3 Pack Monitor Enable
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Recommended System Implementation
        1. 8.1.1.1 The bq76200 is a Slave Device
        2. 8.1.1.2 Flexible Control via AFE or via MCU
        3. 8.1.1.3 Scalable VDDCP Capacitor to Support Multiple FETs in Parallel
        4. 8.1.1.4 Pre-Charge and Pre-Discharge Support
        5. 8.1.1.5 Optional External Gate Resistor
        6. 8.1.1.6 Separate Charge and Discharge paths
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Overview

The bq76200 device is a low-power, high-side, N-Channel MOSFET driver for battery-pack protection systems, allowing a low-side battery-protection system to be implemented into a high-side protection system.

High-side charge/discharge FETs offer a huge advantage versus their low-side counterparts; with high-side implementation, a system-side processor can always communicate with the monitor or micro-controller (MCU) within the battery pack, regardless of whether the FETs are on or off — this is not easily supported in a low-side switching architecture due to the lack of a shared ground reference. One key benefit of an ever-present communication link is the ability to read out critical pack parameters despite safety faults, thereby enabling the system to assess pack conditions before determining if normal operation may resume.

The device allows independent control on charging and discharge via the digital enable pins. The device has integrated charge pump which is enabled by the CP_EN pin. The enable inputs, CHG_EN, DSG_EN, and PCHG_EN control the CHG, DSG, and PCHG FET gate drivers, respectively. The enable inputs can be connected to low-side FET driver outputs of an Analog Front End (AFE) such as Texas Instruments bq769x0 series, a general purpose microcontroller, or dedicated battery pack controller such as the bq783xx series.

In normal mode, the AFE or MCU enables the CHG_EN and DSG_EN, turning on the CHG and DSG FET drivers to connect the battery power to the PACK+ terminal. When a fault is detected by the AFE or the microcontroller, it can disable the CHG_EN and/or DSG_EN to open the charge or discharge path for protection. Note that when either the CHG_EN or DSG_EN is enabled, the charge pump will be automatically enabled even if the CP_EN is in the disable state. It is recommended to enable the charge pump via CP_EN pin during system start-up to avoid adding the tCPON time into the FET switching time during normal operation.

A lower charging current is usually applied to a deeply depleted battery pack. The bq76200 PCHG_EN input provides an option to implement a P-Channel MOSFET pre-charge path (current-limited path) in the battery pack.

An AFE usually provides individual cell voltages and/or battery stack voltage measurements, but it is not necessary to have PACK+ voltage measurement. The bq76200 PMON_EN pin, when enabled, will connect the PACK+ voltage onto the PACKDIV pin, which is connected to an external resistor divider to scale down the PACK+ voltage. This scaled down PACK+ voltage can be connected to a microcontroller's ADC input for voltage measurement. The system can use this information for charger detection or to implement advanced charging control.

For safety purposes, all the enable inputs are internally pulled down. If the AFE or microcontroller is turned off, or if the PCB trace is damaged, the internal pull down of the enable inputs will keep CHG, DSG, PCHG in an off state and the PACK+ voltage does not switch onto the PACKDIV pin.