JAJSG82A November   2015  – September 2018

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Charge Pump Control
      2. 7.3.2 Pin Enable Controls
        1. 7.3.2.1 External Control of CHG and DSG Output Drivers
        2. 7.3.2.2 External Control of PCHG Output Driver
        3. 7.3.2.3 Pack Monitor Enable
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Recommended System Implementation
        1. 8.1.1.1 The bq76200 is a Slave Device
        2. 8.1.1.2 Flexible Control via AFE or via MCU
        3. 8.1.1.3 Scalable VDDCP Capacitor to Support Multiple FETs in Parallel
        4. 8.1.1.4 Pre-Charge and Pre-Discharge Support
        5. 8.1.1.5 Optional External Gate Resistor
        6. 8.1.1.6 Separate Charge and Discharge paths
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

PW Package
16-pin TSSOP
Top View
bq76200 Package.gif

Pin Functions

PIN TYPE(1) DESCRIPTION
NAME NO. I/O
BAT 2 P Top of battery stack
CHG(2) 16 O Gate drive for charge FET
CHG_EN(3) 4 I Charge FET enable
CP_EN(3) 5 I Charge pump enable (internally logic OR'ed with CHG_EN and DSG_EN signals)
DSG(2) 12 O Gate drive for discharge FET
DSG_EN(3) 6 I Discharge FET enable
NC 3, 13, 15 — No connect. Leave the pin floating
PACK 11 P Analog input from PACK+ terminal
PACKDIV(2) 10 O PACK voltage after internal switch (Connect to MCU ADC via resistor divider.)
PCHG(2) 14 O Gate drive for pre-charge FET
PCHG_EN(3) 8 I Pre-charge FET enable
PMON_EN(3) 7 I Pack monitor enable (allows connection of internal switch between PACK and PACKDIV)
VDDCP 1 O Charge pump output. Connect a capacitor to BAT pin. Do not load this pin.
VSS 9 P Ground reference
(1) P = Power Connection, O = Digital Output, AI = Analog Input, I = Digital Input, I/OD = Digital Input/Output
(2) Leave the pin float if function is not used.
(3) Recommended to connect the pin to ground if function is not used.