JAJSIJ8H November   1998  – February 2020 CD4066B

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     デジタル制御ロジックによる双方向信号伝送
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 コミュニティ・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • D|14
  • PW|14
  • NS|14
  • N|14
サーマルパッド・メカニカル・データ
発注情報

7 Parameter Measurement Information

CD4066B Figure_6_schs051.gifFigure 7. Determination of ron as a Test Condition for Control-Input High-Voltage (VIHC) Specification
CD4066B meas_cir_chs383.gifFigure 8. Channel On-State Resistance Measurement Circuit
CD4066B on_chr_chs383.gif
Figure 9. Typical On Characteristics for One of Four Channels
CD4066B off_swt_chs383.gifFigure 10. Off-Switch Input or Output Leakage
CD4066B delay_tim_chs383.gif
Figure 11. Propagation Delay Time Signal Input
(Vis) to Signal Output (Vos)
CD4066B crosstalk_chs383.gifFigure 12. Crosstalk-Control Input to Signal Output
CD4066B Figure_14_schs051.gif
All unused pins are connected to VSS.
Delay is measured at Vos level of +10% from ground (turn-on) or on-state output level (turn-off).
Figure 13. Propagation Delay, tPLH, tPHL Control-Signal Output
CD4066B Figure_15_schs051.gif
All unused pins are connected to VSS.
Figure 14. Maximum Allowable Control-Input Repetition Rate
CD4066B tst_cir_chs383.gifFigure 15. Input Leakage-Current Test Circuit
CD4066B Figure_17_schs051.gifFigure 16. Four-Channel PAM Multiplex System Diagram