JAJSLB2D november   2014  – april 2023 DLP9500UV

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Storage Conditions
    3. 7.3  ESD Ratings
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Thermal Information
    6. 7.6  Electrical Characteristics
    7. 7.7  LVDS Timing Requirements
    8. 7.8  LVDS Waveform Requirements
    9. 7.9  Serial Control Bus Timing Requirements
    10. 7.10 Systems Mounting Interface Loads
    11. 7.11 Micromirror Array Physical Characteristics
    12. 7.12 Micromirror Array Optical Characteristics
    13. 7.13 Chipset Component Usage Specification
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DLPC410 - Digital Controller for DLP Discovery 4100 Chipset
      2. 8.3.2 DLPA200 - DMD Micromirror Drivers
      3. 8.3.3 DLPR410 - PROM for DLP Discovery 4100 Chipset
      4. 8.3.4 DLP9500 - DLP 0.95 1080p 2xLVDS UV Type-A DMD 1080p DMD
        1. 8.3.4.1 DLP9500UV 1080p Chipset Interfaces
          1. 8.3.4.1.1 DLPC410 Interface Description
            1. 8.3.4.1.1.1 DLPC410 IO
            2. 8.3.4.1.1.2 Initialization
            3. 8.3.4.1.1.3 DMD Device Detection
            4. 8.3.4.1.1.4 Power Down
          2. 8.3.4.1.2 DLPC410 to DMD Interface
            1. 8.3.4.1.2.1 DLPC410 to DMD IO Description
            2. 8.3.4.1.2.2 Data Flow
          3. 8.3.4.1.3 DLPC410 to DLPA200 Interface
            1. 8.3.4.1.3.1 DLPA200 Operation
            2. 8.3.4.1.3.2 DLPC410 to DLPA200 IO Description
          4. 8.3.4.1.4 DLPA200 to DLP9500UV Interface
            1. 8.3.4.1.4.1 DLPA200 to DLP9500UV Interface Overview
      5. 8.3.5 Measurement Conditions
    4. 8.4 Device Functional Modes
      1. 8.4.1 Single Block Mode
      2. 8.4.2 Dual Block Mode
      3. 8.4.3 Quad Block Mode
      4. 8.4.4 Global Block Mode
    5. 8.5 Window Characteristics and Optics
      1. 8.5.1 Optical Interface and System Image Quality
      2. 8.5.2 Numerical Aperture and Stray Light Control
      3. 8.5.3 Pupil Match
      4. 8.5.4 Illumination Overfill
    6. 8.6 Micromirror Array Temperature Calculation
      1. 8.6.1 Thermal Test Points
      2. 8.6.2 Micromirror Array Temperature Calculation - Lumens Based
      3. 8.6.3 Micromirror Array Temperature Calculation - Power Density Based
      4. 8.6.4 59
    7. 8.7 Micromirror Landed-On and Landed-Off Duty Cycle
      1. 8.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 8.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 8.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 8.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 DMD Reflectivity Characteristics
        1. 9.1.1.1 Design Considerations Influencing DMD Reflectivity
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Device Description
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Power-Up Sequence (Handled by the DLPC410)
    2. 10.2 DMD Power-Up and Power-Down Procedures
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Impedance Requirements
      2. 11.1.2 PCB Signal Routing
      3. 11.1.3 Fiducials
      4. 11.1.4 PCB Layout Guidelines
        1. 11.1.4.1 DMD Interface
          1. 11.1.4.1.1 Trace Length Matching
        2. 11.1.4.2 DLP9500UV Decoupling
          1. 11.1.4.2.1 Decoupling Capacitors
        3. 11.1.4.3 VCC and VCC2
        4. 11.1.4.4 DMD Layout
        5. 11.1.4.5 DLPA200
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
      2. 12.1.2 Device Marking
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 用語集
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

Pin Functions

PIN (1)TYPE
(I/O/P)		SIGNALDATA RATE (2)INTERNAL
TERM (3)		CLOCKDESCRIPTIONTRACE
(MILS)
NAMENO.
DATA BUS A
D_AN(0)F2InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_AInput data bus A
(2x LVDS)		512.01
D_AN(1)H8InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_A158.79
D_AN(2)E5InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_A471.24
D_AN(3)G9InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_A159.33
D_AN(4)D2InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_A585.41
D_AN(5)G3InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_A551.17
D_AN(6)E11InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_A229.41
D_AN(7)F8InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_A300.54
D_AN(8)C9InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_A346.35
D_AN(9)H2InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_A782.27
D_AN(10)B10InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_A451.52
D_AN(11)G15InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_A74.39
D_AN(12)D14InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_A194.26
D_AN(13)F14InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_A148.29
D_AN(14)C17InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_A244.9
D_AN(15)H16InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_A73.39
D_AP(0)F4InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_A509.63
D_AP(1)H10InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_A152.59
D_AP(2)E3InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_A464.09
D_AP(3)G11InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_A152.39
D_AP(4)D4InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_A591.39
D_AP(5)G5InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_A532.16
D_AP(6)E9InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_A230.78
D_AP(7)F10InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_A300.61
D_AP(8)C11InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_A338.16
D_AP(9)H4InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_A773.17
D_AP(10)B8InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_A449.57
D_AP(11) H14 Input LVCMOS DDR Differentially terminated – 100 Ω DCLK_A Input data bus A
(2x LVDS)		 71.7
D_AP(12) D16 Input LVCMOS DDR Differentially terminated – 100 Ω DCLK_A 198.69
D_AP(13)F16InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_A143.72
D_AP(14)C15InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_A240.14
D_AP(15)G17InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_A74.05
DATA BUS B
D_BN(0)AH2InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_BInput data bus B
(2x LVDS)		525.25
D_BN(1)AD8InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_B190.59
D_BN(2)AJ5InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_B525.25
D_BN(3)AE3InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_B494.91
D_BN(4)AG9InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_B222.67
D_BN(5)AE11InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_B205.45
D_BN(6)AH10InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_B309.05
D_BN(7)AF10InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_B285.62
D_BN(8)AK8InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_B483.58
D_BN(9)AG5InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_B711.58
D_BN(10)AL11InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_B462.21
D_BN(11)AE15InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_B74.39
D_BN(12)AH14InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_B194.26
D_BN(13)AF14InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_B156
D_BN(14)AJ17InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_B247.9
D_BN(15)AD16InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_B111.52
D_BP(0)AH4InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_B525.02
D_BP(1)AD10InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_B190.61
D_BP(2)AJ3InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_B524.22
D_BP(3)AE5InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_B476.07
D_BP(4)AG11InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_B222.8
D_BP(5)AE9InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_B219.48
D_BP(6)AH8InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_B306.55
D_BP(7)AF8InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_B298.04
D_BP(8)AK10InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_B480.31
D_BP(9) AG3 Input LVCMOS DDR Differentially terminated – 100 Ω DCLK_B Input data bus B
(2x LVDS)		 727.18
D_BP(10)AL9InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_B461.02
D_BP(11)AD14InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_B71.35
D_BP(12)AH16InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_B197.69
D_BP(13)AF16InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_B150.38
D_BP(14)AJ15InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_B243.14
D_BP(15)AE17InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_B113.36
DATA BUS C
D_CN(0)B14InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_CInput data bus C
(2x LVDS)		459.04
D_CN(1)E15InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_C342.79
D_CN(2)A17InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_C456.22
D_CN(3)G21InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_C68.24
D_CN(4)B20InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_C362.61
D_CN(5)F20InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_C163.07
D_CN(6)D22InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_C204.16
D_CN(7)G23InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_C105.59
D_CN(8)B26InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_C450.51
D_CN(9)F28InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_C302.04
D_CN(10)C29InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_C429.8
D_CN(11)G27InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_C317.1
D_CN(12)D26InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_C276.76
D_CN(13)H28InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_C186.78
D_CN(14)E29InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_C311.3
D_CN(15)J29InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_C262.62
D_CP(0)B16InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_C463.64
D_CP(1)E17InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_C347.65
D_CP(2)A15InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_C456.45
D_CP(3)H20InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_C67.72
D_CP(4)B22InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_C362.76
D_CP(5)F22InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_C161.69
D_CP(6)D20InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_CInput data bus C
(2x LVDS)		195.09
D_CP(7)H22InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_C104.86
D_CP(8)B28InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_C451.41
D_CP(9)F26InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_C294.22
D_CP(10)C27InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_C429.68
D_CP(11)G29InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_C314.98
D_CP(12)D28InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_C276.04
D_CP(13)H26InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_C186.25
D_CP(14)E27InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_C312.07
D_CP(15)J27InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_C262.94
DATA BUS D
D_DN(0)AK14InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_DInput data bus D
(2x LVDS)		492.53
D_DN(1)AG15InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_D342.78
D_DN(2)AL17InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_D491.83
D_DN(3)AE21InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_D74.24
D_DN(4)AK20InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_D356.23
D_DN(5)AF20InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_D163.07
D_DN(6)AH22InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_D204.16
D_DN(7)AE23InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_D105.59
D_DN(8)AK26InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_D450.51
D_DN(9)AF28InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_D302.04
D_DN(10)AJ29InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_D429.8
D_DN(11)AE27InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_D298.87
D_DN(12)AH26InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_DInput data bus D
(2x LVDS)		276.76
D_DN(13)AD28InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_D186.78
D_DN(14)AG29InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_D311.3
D_DN(15)AC29InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_D262.62
D_DP(0)AK16InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_D495.13
D_DP(1)AG17InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_D342.47
D_DP(2)AL15InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_D492.06
D_DP(3)AD20InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_D67.72
D_DP(4)AK22InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_D356.37
D_DP(5)AF22InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_D161.98
D_DP(6)AH20InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_D195.09
D_DP(7)AD22InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_D102.86
D_DP(8)AK28InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_D451.41
D_DP(9)AF26InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_D296.7
D_DP(10)AJ27InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_D429.68
D_DP(11)AE29InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_D302.74
D_DP(12)AH28InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_D276.04
D_DP(13)AD26InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_D186.25
D_DP(14)AG27InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_D312.07
D_DP(15)AC27InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_D262.94
DATA CLOCKS
DCLK_AND10InputLVCMOS—Differentially terminated – 100 Ω—Input data bus A Clock (2x LVDS)325.8
DCLK_APD8InputLVCMOS—Differentially terminated – 100 Ω—319.9
DCLK_BNAJ11InputLVCMOS—Differentially terminated – 100 Ω—Input data bus B Clock (2x LVDS)318.92
DCLK_BPAJ9InputLVCMOS—Differentially terminated – 100 Ω—318.74
DCLK_CNC23InputLVCMOS—Differentially terminated – 100 Ω—Input data bus C Clock (2x LVDS)252.01
DCLK_CPC21InputLVCMOS—Differentially terminated – 100 Ω—241.18
DCLK_DNAJ23InputLVCMOS—Differentially terminated – 100 Ω—Input data bus D Clock (2x LVDS)252.01
DCLK_DPAJ21InputLVCMOS—Differentially terminated – 100 Ω—241.18
DATA CONTROL INPUTS
SCTRL_ANJ3InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_ASerial control for data bus A (2x LVDS)608.14
SCTRL_APJ5InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_A607.45
SCTRL_BNAF4InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_BSerial control for data bus B (2x LVDS)698.12
SCTRL_BPAF2InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_B703.8
SCTRL_CNE23InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_CSerial control for data bus C (2x LVDS)232.46
SCTRL_CPE21InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_C235.21
SCTRL_DNAG23InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_DSerial control for data bus D (2x LVDS)235.53
SCTRL_DPAG21InputLVCMOSDDRDifferentially terminated – 100 ΩDCLK_D235.66
SERIAL COMMUNICATION AND CONFIGURATION
SCPCLKAE1InputLVCMOS—pull-down—Serial port clock324.26
SCPDOAC3OutputLVCMOS——SCP_CLKSerial port output281.38
SCPDIAD2InputLVCMOS—pull-downSCP_CLKSerial port input261.55
SCPENAD4InputLVCMOS—pull-downSCP_CLKSerial port enable184.86
PWRDNB4InputLVCMOS—pull-down—Device reset458.78
MODE_AJ1InputLVCMOS—pull-down—Data bandwidth mode select471.57
MODE_BG1InputLVCMOS—pull-down—521.99
MICROMIRROR CLOCKING PULSE (BIAS RESET)
MBRST(0)L5InputAnalog———Micromirror clocking pulse reset MBRST signals clock micromirrors into state of LVCMOS memory cell associated with each mirror.898.97
MBRST(1)M28InputAnalog———621.98
MBRST(2)P4InputAnalog———846.88
MBRST(3)P30InputAnalog———784.18
MBRST(4)L3InputAnalog———763.34
MBRST(5)P28InputAnalog———749.61
MBRST(6)P2InputAnalog———878.25
MBRST(7)T28InputAnalog———783.83
MBRST(8)M4InputAnalog———969.36
MBRST(9)L29InputAnalog———621.24
MBRST(10)T4InputAnalog———918.43
MBRST(11)N29InputAnalog———685.14
MBRST(12)N3InputAnalog———812.31
MBRST(13)L27InputAnalog———591.89
MBRST(14)R3InputAnalog———878.5
MBRST(15)V28InputAnalog———660.15
MBRST(16)V4InputAnalog———848.64
MBRST(17)R29InputAnalog———796.31
MBRST(18)Y4InputAnalog———715
MBRST(19)AA27InputAnalog———604.35
MBRST(20)W3InputAnalog———832.39
MBRST(21)W27InputAnalog———675.21
MBRST(22)AA3InputAnalog———861.18
MBRST(23)W29InputAnalog———662.66
MBRST(24)U5InputAnalog———850.06
MBRST(25)U29InputAnalog———726.56
MBRST(26)Y2InputAnalog———861.48
MBRST(27)AA29InputAnalog———683.83
MBRST(28)U3InputAnalog———878.5
MBRST(29)Y30InputAnalog———789.2
POWER
VCCA3, A5, A7, A9, A11, A13, A21, A23, A25, A27, A29, B2,PowerAnalog———Power for LVCMOS logic—
C1, C31, E31, G31, J31, K2, L31, N31, R31, U31, W31,
AA31, AC1, AC31, AE31, AG1, AG31, AJ31, AK2,
AK30, AL3, AL5, AL7, AL19, AL21, AL23, AL25, AL27
VCCIH6, H12, H18, H24, M6, M26, P6, P26, T6, T26, V6, V26,PowerAnalog———Power supply for LVDS Interface—
Y6, Y26, AD6, AD12, AD18, AD24
VCC2L1, N1, R1, U1, W1, AA1PowerAnalog———Power for high voltage CMOS logic—
VSSA1, B12, B18, B24, B30, C7, C13, C19, C25, D6, D12,PowerAnalog———Common return for all power inputs—
D18, D24, D30, E1, E7, E13, E19, E25, F6, F12, F18, F24,
F30, G7, G13, G19, G25, K4, K6, K26, K28, K30, M2, M30,
N5, N27, R5, T2, T30, U27, V2, V30, W5, Y28, AB2, AB4,
AB6, AB26, AB28, AB30, AD30, AE7, AE13, AE19,
AE25, AF6, AF12, AF18, AF24, AF30, AG7, AG13,
AG19, AG25, AH6, AH12, AH18, AH24, AH30, AJ1,
AJ7, AJ13, AJ19, AJ25, AK6, AK12, AK18, AL29
RESERVED SIGNALS (NOT FOR USE IN SYSTEM)
RESERVED_FCJ7InputLVCMOS—pull-down—Pins should be connected to VSS—
RESERVED_FDJ9InputLVCMOS—pull-down——
RESERVED_PFEJ11InputLVCMOS—pull-down——
RESERVED_STMAC7InputLVCMOS—pull-down——
RESERVED_AEC3InputLVCMOS—pull-down——
NO_CONNECTA19, B6, C5, H30, J13, J15, J17, J19, J21, J23, J25, R27,—————No connection (any connection to these terminals may result in undesirable effects)—
AA5, AC11, AC13, AC15, AC17, AC19, AC21, AC23,
AC25, AC5, AC9, AK24, AK4, AL13
(1) The following power supplies are required to operate the DMD: VCC, VCC1, VCC2. VSS must also be connected.
(2) DDR = Double Data Rate. SDR = Single Data Rate. Refer to the Section 7.7 for specifications and relationships.
(3) Refer to Section 7.6 for differential termination specification.