JAJSSZ1 データシート

JAJSSZ1 December 2023 DRV8334

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

PHP|48
- MPQF051B

サーマルパッド・メカニカル・データ

PHP|48
- PPTD389

発注情報

jajssz1_oa

7.6.2 CONTROL Registers

Table 7-15 lists the memory-mapped registers for the CONTROL registers. All register offset addresses not listed in Table 7-15 should be considered as reserved locations and the register contents should not be modified.

Table 7-15 CONTROL Registers

Address	Acronym	Register Name	Section
1Ah	IC_CTRL1	IC Control Register 1	Section 7.6.2.1
1Bh	IC_CTRL2	IC Control Register 2	Section 7.6.2.2
1Ch	IC_CTRL3	IC Control Register 3	Section 7.6.2.3
1Eh	GD_CTRL1	Gate Drive Control Register 1	Section 7.6.2.4
1Fh	GD_CTRL2	Gate Drive Control Register 2	Section 7.6.2.5
21h	GD_CTRL3	Gate Drive Control Register 3	Section 7.6.2.6
22h	GD_CTRL3B	Gate Drive Control Register 3B	Section 7.6.2.7
23h	GD_CTRL4	Gate Drive Control Register 4	Section 7.6.2.8
24h	GD_CTRL5	Gate Drive Control Register 5	Section 7.6.2.9
25h	GD_CTRL6	Gate Drive Control Register 6	Section 7.6.2.10
26h	GD_CTRL7	Gate Drive Control Register 7	Section 7.6.2.11
29h	CSA_CTRL	CSA Control Register	Section 7.6.2.12
2Bh	MON_CTRL1	Monitor Control Register 1	Section 7.6.2.13
2Ch	MON_CTRL2	Monitor Control Register 2	Section 7.6.2.14
2Dh	MON_CTRL3	Monitor Control Register 3	Section 7.6.2.15
2Eh	MON_CTRL4	Monitor Control Register 4	Section 7.6.2.16
2Fh	MON_CTRL5	Monitor Control Register 5	Section 7.6.2.17
30h	MON_CTRL6	Monitor Control Register 6	Section 7.6.2.18

Complex bit access types are encoded to fit into small table cells. Table 7-16 shows the codes that are used for access types in this section.

Table 7-16 CONTROL Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
R-0	R -0	Read Returns 0s
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value

7.6.2.1 IC_CTRL1 Register (Address = 1Ah) [Reset = 0000h]

IC_CTRL1 is shown in Table 7-17.

Return to the Summary Table.

Table 7-17 IC_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-1	RESERVED	R	0h	Reserved
0	VDDSDO_SEL	R/W	0h	VDDSDO regulator output selection bit. The bit determines VOH level of SDO and PHCx between 3.3V mode or 5V mode. The VIH/VIL of input buffers will not be affected by VDDSDO_SEL bit. Before VDDSDO_SEL is set, VDDSDO_MON_LVL needs to be correctly configured. 0b = SDO/PHCx 3.3V mode 1b = SDO/PHCx 5V mode

7.6.2.2 IC_CTRL2 Register (Address = 1Bh) [Reset = 0006h]

IC_CTRL2 is shown in Table 7-18.

Return to the Summary Table.

Table 7-18 IC_CTRL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	ENABLE_DRV	R/W	0h	Enable predriver bit. The bit is cleared to 0b if one or multiple predriver shutdown conditions are detected and fault flags are set to 1b and if ALL_CH is 1b, or if DRVOFF is driven high. The ENABLE_DRV bit is forced to 0b by device while the fault condition exists or while DRVOFF is high. At power up, write access to ENABLE_DRV is ignored and the bit cannot be set to 1 until nFAULT goes high. After nFAULT goes high, wait 5us and set ENABLE_DRV to 1b. During initial setup, it's recommended to set the gate drive current IDRVx settings before ENABLE_DRV is set to 1b. 0b = INHx and INLx digital inputs are ignored and the gate driver outputs are pulled low (active pull down) by default. 1b = Gate driver outputs are controlled by INHx and INL digital inputs. If IDRVP or IDRVN register values is modified while ENABLE_DRV is 1b, the one PWM cycle delay is expected to get the gate driver current updated.
14-12	RESERVED	R	0h	Reserved
11	CSA_EN	R/W	0h	Current Sense Amplifier Enable. If GVDD_UV_MODE is 0b (Warning mode), MCU must ensure GVDD_UV flag is 0b before CSA_EN bit is set to 1b. If GVDD_UV_MODE is 1b (Fault mode), IC disables CSA amplifier when GVDD_UV is detected. 0b = CSA is disabled. SOx are HiZ state. 1b = CSA is enabled.
10	CSA_AZ_DIS	R/W	0h	Current Sense Amplifier Auto Zero function disable 0b = CSA Auto Zero function is enabled. This bit should be 0b during normal PWM/CSA operation. 1b = CSA Auto Zero function is disabled. The purpose of this bit is to disable switching activity of current sense amplifier for auto zero function. Refer to timing requirements if this bit is used.
9	DIS_GVDD_SS	R/W	0h	Note: TI recommends users to set DIS_GVDD_SS to 1b after power up. Disable GVDD Charge pump soft start 0b = GVDD output load capability will not meet the spec when PVDD input voltage is lower than 7.2V. 1b = TI recommends users to set the bit to 1 after power up.
8	GVDD_MODE	R/W	0h	GVDD Charge pump LDO mode control 0b = Normal GVDD operation. Charge pump mode and LDO mode are controlled by device. 1b = LDO mode. GVDD charge pump clock is disabled. (charge pump switching operation is disabled).
7-6	VCP_MODE	R/W	0h	VCP/TCP mode control 00b = Normal VCP/TCP operation. VCP/TCP is enabled at power up. TCP SW is enabled when SPI ENABLE_DRV is 0. When DRVOFF is high and if system expects the device to keep BST cap stay charged, VCP_MODE must be 00b. 01b = VCP/CPTH-SHx switch is disabled. VCP/TCP charge pump clock is active. This bit is valid regardless of SPI ENABLE_DRV. 10b = VCP/TCP shutdown. Both VCP/CPTH-SHx switch and VCP/TCP charge pump clock are disabled. This bit is valid regardless of SPI ENABLE_DRV. 11b = Normal VCP/TCP operation. VCP/TCP is enabled at power up. TCP SW is disabled when SPI ENABLE_DRV is 0.
5-4	RESERVED	R	0h	Reserved
3-1	LOCK	R/W	3h	Lock and unlock the register setting Bit settings not listed have no effect. 011b = Unlock all the registers 110b = Lock the settings by ignoring further register writes except to these bits.
0	CLR_FLT	R/W	0h	Clear fault. After fault event is detected and fault flag is set, it's recommended to issue CLR_FLT command first, then ENABLE_DRV command next in a separate SPI frame. If CLR_FLT and ENABLE_DRV commands are issued in the same SPI frame, CLR_FLT is higher priority and ENABLE_DRV will not be set if fault flag is already latched and the device is waiting CLR_FLT. 0b = No action 1b = Clear faults. Self-clear to 0b.

7.6.2.3 IC_CTRL3 Register (Address = 1Ch) [Reset = 8001h]

IC_CTRL3 is shown in Table 7-19.

Return to the Summary Table.

Table 7-19 IC_CTRL3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	SPI_CRC_EN	R/W	1h	SPI CRC Enable 0b = SPI CRC is disabled. One SPI frame is 8-bit command, 16-bit data. 1b = SPI CRC is enabled. One SPI frame is 8-bit command, 16-bit data, and 8-bit CRC.
14	WARN_MODE	R/W	0h	Warning nFAULT mode; Control nFAULT response for warning events 0b = No nFAULT reporting for warning response. Status flags are set. 1b = nFAULT is driven low for warning response. Status flags are set.
13	RESERVED	R	0h	Reserved
12	DIS_SSC	R/W	0h	TI Internal design parameter: No change is required unless notified by TI. The bit disables Spread Spectrum Clocking feature of the device internal oscillator 0b = Normal operation. Spread Spectrum Clocking feature is enabled. 1b = Spread Spectrum Clock feature is disabled for TI debug purpose.
11	RESERVED	R	0h	Reserved
10	TCP_EN_DLY	R/W	0h	Delay time to activate trickle charge pump after the device detects PWM inactive (INHx=INLx=Low) 0b = 100us (typ) 1b = 250us (typ)
9-2	RESERVED	R	0h	Reserved
1-0	OTSD_MODE	R/W	1h	Overtemperature shutdown mode 00b = Warning mode 01b = Fault (shutdown) mode 10b = No report. No shutdown. 11b = No report. No shutdown

7.6.2.4 GD_CTRL1 Register (Address = 1Eh) [Reset = 0138h]

GD_CTRL1 is shown in Table 7-20.

Return to the Summary Table.

Table 7-20 GD_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14-12	PWM_MODE	R/W	0h	PWM mode. 000b = 6x PWM mode (INHx/INLx) 001b = 3x PWM mode with INLx enable control 010b = 3x PWM mode with SPI enable control (DRVEN_x). INLx don't affect PWM control. MCU must use this mode to generate PWM if PHC_OUTEN is 1b. 011b = 1x PWM mode (INHx/INLx) 100b = Reserved. 101b = SPI Gate Drive Mode. DRV_GHx and DRV_GLx register bits are valid. 110b = 6x PWM mode (INHx/INLx) 111b = 6x PWM mode (INHx/INLx)
11	RESERVED	R	0h	Reserved
10-9	SGD_MODE	R/W	0h	Smart Gate Drive mode 00b = Smart Gate Drive with fixed peak current control. TDRVN_D is not valid and ignored. 01b = Smart Gate Drive with dynamic peak current control. TDRVN_D is enabled.
8	SGD_TMP_EN	R/W	1h	Enable dynamic temperature control of Smart Gate Drive. 0b = SGD temperature control is disabled. IDRVP and IDRVN are constant. 1b = SGD temperature control is enabled. IDRVP (300mA or higher) and IDRVN (600mA or higher) are adjusted based on DIE_TEMP information. The IDRIVx adjustment takes place every 9ms by the device or when the SGD_TMP_EN bit changes from 0b to 1b.
7	STP_MODE	R/W	0h	Shoot-through protection report mode Note: Other than PWM_MODE 000b, STP_MODE shall be set to 1b, otherwise a false STP_FLT flag will be reported. 0b = Shoot-through protection is enabled. The gate driver outputs are forced low during a shoot-through condition. The SPI fault flag is set and the nFAULT pin is driven low when the condition is detected. Set STP_MODE to 0b only for PWM_MODE 000b (6xPWM mode). 1b = Shoot-through protection is enabled but no reporting is performed. The gate driver outputs are forced low during a shoot-through condition. No SPI fault flag is set, and the nFAULT pin stays high when the condition is detected. Other than PWM_MODE 000b, STP_MODE shall be set to 1b not to report a false STP_FLT flag.
6	RESERVED	R	0h	Reserved
5-3	DEADT	R/W	7h	Gate driver dead time 000b = 70ns 001b = 200 ns 010b = 300 ns 011b = 500 ns 100b = 750 ns 101b = 1000 ns 110b = 1500 ns 111b = 2000 ns
2	DEADT_MODE	R/W	0h	Dead Time Insertion Mode. 0b = Dead time is inserted when device input (INHx or INLx) goes low. 1b = Dead time is inserted by monitoring gate driver outputs (GHx or GLx).
1-0	DEADT_MODE_6X	R/W	0h	Dead Time Violation Response Mode for 6 PWM mode only. NOTE: Other than 6 PWM mode, dead time is always inserted regardless of the DEADT_MODE bit and no fault is reported to the MCU. 00b = Dead-time protection is enabled. The gate driver control signals are enforced low during the dead time period. The SPI fault flag is set and the nFAULT pin is driven low when the dead time condition is detected. 01b = Dead-time protection is enabled but no reporting is performed. The gate driver outputs are forced low during the dead time period. The SPI fault flag is never set and the nFAULT pin stays high when the dead time condition is detected 10b = Dead-time protection is disabled. No dead time is inserted. No SPI fault flag is set and the nFAULT1 pin stays high. This is applied to both the cases when DEADT_MODE is 0b (monitoring INH or INL) and 1b (monitoring GHx or GLx). 11b = Dead-time protection is enabled and SPI fault is set but no nFAULT reporting is performed. The gate driver outputs are forced low during the dead time period. The nFAULT pin stays high when the dead time condition is detected.

7.6.2.5 GD_CTRL2 Register (Address = 1Fh) [Reset = 0717h]

GD_CTRL2 is shown in Table 7-21.

Return to the Summary Table.

Table 7-21 GD_CTRL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	RESERVED	R	0h	Reserved
11-8	TDRVP	R/W	7h	Peak source pull up drive timing 0000b = 0.143 us 0001b = 0.179 us 0010b = 0.321 us 0011b = 0.464 us 0100b = 0.607 us 0101b = 0.750 us 0110b = 0.893 us 0111b = 1.036 us 1000b = 1.321 us 1001b = 1.607 us 1010b = 1.893 us 1011b = 2.179 us 1100b = 2.536 us 1101b = 2.964 us 1110b = 3.393 us 1111b = 3.821 us
7-4	TDRVN_D	R/W	1h	Peak sink pull down pre-discharge timing 0000b = 70 ns 0001b = 140 ns 0010b = 211 ns 0011b = 281 ns 0100b = 351 ns 0101b = 421 ns 0110b = 491 ns 0111b = 561 ns 1000b = 632 ns 1001b = 702 ns 1010b = 772 ns 1011b = 842 ns 1100b = 912 ns 1101b = 982 ns 1110b = 1053 ns 1111b = 1123 ns
3-0	TDRVN	R/W	7h	Peak sink pull down drive timing. Refer to TDRVP

7.6.2.6 GD_CTRL3 Register (Address = 21h) [Reset = 0700h]

GD_CTRL3 is shown in Table 7-22.

Return to the Summary Table.

Table 7-22 GD_CTRL3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	RESERVED	R	0h	Reserved
11-8	TDRVN_SDD	R/W	7h	Smart shutdown discharge timing. Refer to TDRVN_D
7-6	RESERVED	R	0h	Reserved
5-0	IDRVN_SD	R/W	0h	Smart shutdown drive current.

7.6.2.7 GD_CTRL3B Register (Address = 22h) [Reset = 0000h]

GD_CTRL3B is shown in Table 7-23.

Return to the Summary Table.

Table 7-23 GD_CTRL3B Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	RESERVED	R	0h	Reserved
13-8	IDRVN_D_H	R/W	0h	Peak sink pull down pre-discharge current for high-side gate driver. Refer to IDRIVE description
7-6	RESERVED	R	0h	Reserved
5-0	IDRVN_D_L	R/W	0h	Peak sink pull down pre-discharge current for low-side gate driver. Refer to IDRIVE description

7.6.2.8 GD_CTRL4 Register (Address = 23h) [Reset = 0000h]

GD_CTRL4 is shown in Table 7-24.

Return to the Summary Table.

Table 7-24 GD_CTRL4 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	PWM1X_COM	R/W	0h	1x PWM Commutation Control 0b = 1x PWM mode uses synchronous rectification 1b = 1x PWM mode uses asynchronous rectification
14	PWM1X_DIR	R/W	0h	1x PWM Direction. In 1x PWM mode this bit is ORed with the INHC (DIR) input
13-12	PWM1X_BRAKE	R/W	0h	1x PWM output configuration 00b = Outputs follow commanded inputs 01b = Turn on all three low-side MOSFETs 10b = Turn on all three high-side MOSFETs 11b = Turn off all six MOSFETs (coast)
11-10	RESERVED	R	0h	Reserved
9	IDRVP_CFG	R/W	0h	IDRVP configuration mode 0b = IDRVP register is not valid and ignored. IDRV_RATIO is used to determine IDRVP parameter if IDRVN is in the range of 000000b (0.7mA) - 100011b (247mA). If IDRVN is 100100b (600mA) - 101100b (2000mA), IDRVP uses the same setting as IDRVN. For example, if IDRVN is set to 100100b (600mA), IDRVP is 100100b (300mA) where pull-up current is typically half of pull-down current. 1b = IDRVP register is used to determine IDRVP parameter. IDRV_RATIO is not valid and is ignored.
8	IHOLD_SEL	R/W	0h	Select IHOLD pull-up and pull-down current. IHOLD_SEL bit must be configured while PWM is inactive (ENABLE_DRV is 0b). 0b = IHOLD pull-up/down 500mA/1000mA (typ) 1b = IHOLD pull-up/down 260mA/260mA (typ)
7-6	RESERVED	R	0h	Reserved
5	DRV_GHA	R/W	0h	Drive GHA by SPI command. PWM_MODE = 101b (SPI gate drive mode) only. This bit is valid when ENABLE_DRV is 1b. 0b = GHA is driven low 1b = GHA is driven high
4	DRV_GHB	R/W	0h	Drive GHB by SPI command. PWM_MODE = 101b (SPI gate drive mode) only. This bit is valid when ENABLE_DRV is 1b. 0b = GHB is driven low 1b = GHB is driven high
3	DRV_GHC	R/W	0h	Drive GHC by SPI command. PWM_MODE = 101b (SPI gate drive mode) only. This bit is valid when ENABLE_DRV is 1b. 0b = GHC is driven low 1b = GHC is driven high
2	DRV_GLA	R/W	0h	Drive GLA by SPI command. PWM_MODE = 101b (SPI gate drive mode) only. This bit is valid when ENABLE_DRV is 1b. 0b = GLA is driven low 1b = GLA is driven high
1	DRV_GLB	R/W	0h	Drive GLB by SPI command. PWM_MODE = 101b (SPI gate drive mode) only. This bit is valid when ENABLE_DRV is 1b. 0b = GLB is driven low 1b = GLB is driven high
0	DRV_GLC	R/W	0h	Drive GLC by SPI command. PWM_MODE = 101b (SPI gate drive mode) only. This bit is valid when ENABLE_DRV is 1b. 0b = GLC is driven low 1b = GLC is driven high

7.6.2.9 GD_CTRL5 Register (Address = 24h) [Reset = 0007h]

GD_CTRL5 is shown in Table 7-25.

Return to the Summary Table.

Table 7-25 GD_CTRL5 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-3	RESERVED	R	0h	Reserved
2	DRVEN_A	R/W	1h	DRVEN_A = 0 enforces GHA and GLA low with active pull down without shutdown sequence. This bit is valid for any PWM_MODE settings. This bit is valid when ENABLE_DRV is 1b. 0b = GHA and GLA are actively pulled down (low). ENABLE_DRV is not affected by this bit. 1b = No affect. GHA and GLA are controlled normally depending following PWM_MODE setting.
1	DRVEN_B	R/W	1h	DRVEN_B = 0 enforces GHB and GLB low with active pull down without shutdown sequence. This bit is valid for any PWM_MODE settings. This bit is valid when ENABLE_DRV is 1b. 0b = GHB and GLB are actively pulled down (low). ENABLE_DRV is not affected by this bit. 1b = No affect. GHB and GLB are controlled normally depending following PWM_MODE setting.
0	DRVEN_C	R/W	1h	DRVEN_C = 0 enforces GHC and GLC low with active pull down without shutdown sequence. This bit is valid for any PWM_MODE settings. This bit is valid when ENABLE_DRV is 1b. 0b = GHC and GLC are actively pulled down (low). ENABLE_DRV is not affected by this bit. 1b = No affect. GHC and GLC are controlled normally depending following PWM_MODE setting.

7.6.2.10 GD_CTRL6 Register (Address = 25h) [Reset = 0000h]

GD_CTRL6 is shown in Table 7-26.

Return to the Summary Table.

Table 7-26 GD_CTRL6 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	RESERVED	R	0h	Reserved
13-8	IDRVP_H	R/W	0h	High-side peak source pull up current. IDRVP_H is valid if IDRVP_CFG = 1b. IDRVP_H is not valid and ignored if IDRVP_CFG = 0b.
7-6	RESERVED	R	0h	Reserved
5-0	IDRVP_L	R/W	0h	Low-side peak source pull up current. IDRVP_L is valid if IDRVP_CFG = 1b. IDRVP_H is not valid and ignored if IDRVP_CFG = 0b.

7.6.2.11 GD_CTRL7 Register (Address = 26h) [Reset = 0000h]

GD_CTRL7 is shown in Table 7-27.

Return to the Summary Table.

Table 7-27 GD_CTRL7 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	IDRV_RATIO_H	R/W	0h	High-side IDRVP and IDRVN ratio. IDRV_RATIO_H is valid if IDRVP_CFG = 0b and if the range of IDRVN_H is from 00000b (0.7mA) to 100011b (typ 247mA). IDRIVE_RATIO_H doesn't affect gate driver performance if IDRVN_H is 100100b(600mA) or higher setting. If IDRVP_CFG = 1b, IDRV_RATIO_H is not valid and ignored. 00b = IDRVP is IDRVN x 1 01b = IDRVP is IDRVN x 0.75 10b = IDRVP is IDRVN x 0.5 11b = IDRVP is IDRVN x 0.25
13-8	IDRVN_H	R/W	0h	High-side peak sink pull down current. Refer to Electrical Characteristics table, IDRVN parameter.
7-6	IDRV_RATIO_L	R/W	0h	Low-side IDRVP and IDRVN ratio. IDRV_RATIO_L is valid if IDRVP_CFG = 0b and if the range of IDRVN_H is from 00000b (0.7mA) to 100011b (typ 247mA). IDRIVE_RATIO_L doesn't affect gate driver performance if IDRVN_H is 100100b(600mA) or higher setting. If IDRVP_CFG = 1b, IDRV_RATIO_L is not valid and ignored. 00b = IDRVP is IDRVN x 1 01b = IDRVP is IDRVN x 0.75 10b = IDRVP is IDRVN x 0.5 11b = IDRVP is IDRVN x 0.25
5-0	IDRVN_L	R/W	0h	Low-side peak sink pull down current. Refer to Electrical Characteristics table, IDRVN parameter.

7.6.2.12 CSA_CTRL Register (Address = 29h) [Reset = 0000h]

CSA_CTRL is shown in Table 7-28.

Return to the Summary Table.

Table 7-28 CSA_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
15	AREF_DIV	R/W	0h	VREF dividing ratio 0b = 1/2 1b = 1/8
14-12	RESERVED	R	0h	Reserved
11-8	CSA_GAIN_A	R/W	0h	CSA Gain of SOA. Gain can be updated during PWM operation. Undefined settings (1001b - 1111b) are 40. 0000b = 5 0001b = 10 0010b = 12 0011b = 16 0100b = 20 0101b = 23 0110b = 25 0111b = 30 1000b = 40
7-4	CSA_GAIN_B	R/W	0h	CSA Gain of SOB. Gain can be updated during PWM operation. Undefined settings (1001b - 1111b) are 40. 0000b = 5 0001b = 10 0010b = 12 0011b = 16 0100b = 20 0101b = 23 0110b = 25 0111b = 30 1000b = 40
3-0	CSA_GAIN_C	R/W	0h	CSA Gain of SOC. Gain can be updated during PWM operation. Undefined settings (1001b - 1111b) are 40. 0000b = 5 0001b = 10 0010b = 12 0011b = 16 0100b = 20 0101b = 23 0110b = 25 0111b = 30 1000b = 40

7.6.2.13 MON_CTRL1 Register (Address = 2Bh) [Reset = 4002h]

MON_CTRL1 is shown in Table 7-29.

Return to the Summary Table.

Table 7-29 MON_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	VDRAIN_OV_LVL	R/W	1h	VDRAIN Overvoltage threshold level 00b = 29.5V (typ) 01b = 34.5V (typ) 10b = 53.5V (typ) 11b = 53.5V (typ)
13	VDRAIN_MON_MODE	R/W	0h	VDRAIN monitor mode for under and over voltage monitors 0b = Warning mode 1b = Fault mode
12	BST_OV_MODE	R/W	0h	BST pin overvoltage monitor mode 0b = Warning mode 1b = Fault mode
11	BST_UV_LATCH	R/W	0h	BST pin undervoltage latch mode 0b = BST_UV is real time monitor. BST_UV is cleared to 0b when VBST exceeds VBST_UV threshold. BST_MON_MODE is ignored. 1b = BST_UV is latched when under voltage condition is detected.
10	BST_UV_MODE	R/W	0h	BST pin monitor mode. If BST_UV_LATCH is 1b, BST_UV_MODE determines Warning mode or Fault mode. Refer to BST_UV_LATCH register bit. 0b = Warning mode 1b = Fault mode
9	BST_UV_LVL	R/W	0h	BST pin undervoltage threshold level V_{BST_UV} 0b = 4.2V (typ) 1b = 7.2V (typ)
8	DVDD_OV_MODE	R/W	0h	DVDD monitor mode of over voltage monitor 0b = Warning mode 1b = Fault mode
7	GVDD_OV_MODE	R/W	0h	GVDD monitor mode of over voltage monitor 0b = Warning mode 1b = Fault mode
6	GVDD_UV_MODE	R/W	0h	f 0b = Warning mode 1b = Fault mode
5	VCP_OV_MODE	R/W	0h	VCP monitor mode of over voltage monitor 0b = Warning mode 1b = Fault mode
4	VCP_UV_MODE	R/W	0h	VCP monitor mode of under voltage monitor 0b = Warning mode 1b = Fault mode
3	PVDD_UVW_LVL	R/W	0h	PVDD UV Warning threshold level
2-1	PVDD_OV_LVL	R/W	1h	PVDD OV threshold level
0	PVDD_OV_MODE	R/W	0h	PVDD OV threshold monitor mode 0b = Warning mode 1b = Fault mode

7.6.2.14 MON_CTRL2 Register (Address = 2Ch) [Reset = 1101h]

MON_CTRL2 is shown in Table 7-30.

Return to the Summary Table.

Table 7-30 MON_CTRL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	VDS_MODE	R/W	0h	VDS overcurrent mode 00b = Warning mode. 01b = Fault mode. 10b = Reserved 11b = No report. No shutdown.
13-11	VDS_BLK	R/W	2h	VDS overcurrent blanking time
10-8	VDS_DEG	R/W	1h	VDS overcurrent deglitch time
7-6	VGS_MODE	R/W	0h	VGS monitor mode 00b = Warning mode. 01b = Fault mode. 10b = Reserved 11b = No report. No shutdown.
5-3	VGS_BLK	R/W	0h	VGS monitor blanking time.
2-0	VGS_DEG	R/W	1h	VGS monitor deglitch time

7.6.2.15 MON_CTRL3 Register (Address = 2Dh) [Reset = 003Bh]

MON_CTRL3 is shown in Table 7-31.

Return to the Summary Table.

Table 7-31 MON_CTRL3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-9	RESERVED	R	0h	Reserved
8	VGS_LVL	R/W	0h
7-6	SNS_OCP_MODE	R/W	0h	Monitor mode of V_SENSE overcurrent protection (Rshunt monitor) 00b = Warning mode. 01b = Fault mode. 10b = Reserved 11b = No report. No shutdown.
5-3	SNS_OCP_LVL	R/W	7h	Threshold voltage of V_SENSE overcurrent protection (Rshunt monitor) 000b = 50mV (typ) 001b = 75mV (typ) 010b = 100mV (typ) 011b = 125mV (typ) 100b = 150mV (typ) 101b = 200mV (typ) 110b = 300mV (typ) 111b = 500mV (typ)
2	RESERVED	R	0h	Reserved
1-0	SNS_OCP_DEG	R/W	3h	Deglitch time of V_SENSE overcurrent protection (Rshunt monitor) 00b = 2.0us (typ) 01b = 4.0us (typ) 10b = 6.0us (typ) 11b = 10.0us (typ)

7.6.2.16 MON_CTRL4 Register (Address = 2Eh) [Reset = 0000h]

MON_CTRL4 is shown in Table 7-32.

Return to the Summary Table.

Table 7-32 MON_CTRL4 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-6	RESERVED	R	0h	Reserved
5	WDT_FLT_MODE	R/W	0h	Watchdog Time Fault Mode 0b = Report on nFAULT. No gate driver shutdown. 1b = Report on nFAULT. Gate Driver shutdown.
4	WDT_CNT	R/W	0h	Watchdog Time Fault Count 0b = One time WDT fault reports status flag and asserts nFAULT1 pin low. 1b = Three consecutive faults report status flag and assert nFAULT pin low. Internal counter is cleared to 0 after the three consecutive faults are detected. Internal counter can also be cleared if WDT_EN is cleared to 0b.
3	WDT_MODE	R/W	0h	Watchdog Time MODE 0b = Any valid read access reset the watchdog timer 1b = A valid write access to SPI_TEST resets the watchdog timer
2-1	WDT_W	R/W	0h	HASH(0x27dc9b0) 00b = tWDL 0.5ms tWDU 10ms 01b = tWDL 1ms tWDU 20ms 10b = tWDL 2ms tWDU 40ms 11b = tWDL 2ms tWDU 40ms
0	WDT_EN	R/W	0h	Watchdog Time Enable 0b = Watchdog timer disabled 1b = Watchdog timer enabled

7.6.2.17 MON_CTRL5 Register (Address = 2Fh) [Reset = 0000h]

MON_CTRL5 is shown in Table 7-33.

Return to the Summary Table.

Table 7-33 MON_CTRL5 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	RESERVED	R	0h	Reserved
13	VDDSDO_MON_LVL	R/W	0h	VDDSDO (Power supply of SDO) undervoltage and overvoltage monitor level. The target nominal VDDSDO voltage is either 3.3V or 5V. 0b = 3.3V mode 1b = 5V mode
12	VREF_MON_LVL	R/W	0h	VREF (CSA reference voltage) undervoltage and overvoltage monitor threshold level. The target nominal VREF voltage is either 3.3V or 5V 0b = Target nominal voltage of VREF is 3.3V. The under voltage monitor threshold is 2.8V (typ) and the overvoltage monitor threshold is 3.8V (typ). 1b = Target nominal voltage of VREF is 5V.The under voltage monitor threshold is 4.2V (typ) and the overvoltage monitor threshold is 5.8V (typ).
11	VREF_MON_MODE	R/W	0h	VREF monitor mode for under and over voltage monitors. 0b = Warning mode 1b = Fault mode
10-5	RESERVED	R	0h
4	PHC_OUTDG_SEL	R/W	0h	Phase Comparator output (PHCx device pin) deglitch time selection 0b = No deglitch time. The device comparator output is directly routed to device pin (PHCx). 1b = Deglitch 1us (typ) is enabled, and deglitch is added on the phase comparator output.
3	PHC_MON_MODE	R/W	0h	Phase Comparator fault monitor mode 0b = Report to status register bits. No nFAULT1 reporting. No gate driver shutdown 1b = Report to status register bits and nFAULT1 is driven low. No Gate driver shutdown
2	PHC_COMPEN	R/W	0h	Phase Comparator enable 0b = disabled. Phase comparator outputs (device pin or SPI status bit) are not valid. 1b = enabled. System needs to wait 5us after enabled.
1	PHC_OUTEN	R/W	0h	Phase Output buffer enable. This bit can be enabled regardless of PWM_MODE. 0b = disabled. The output is HiZ. 1b = enabled. INLx signals are tied to low in device.
0	PHC_TH	R/W	0h	Phase Comparator threshold 0b = 75% for rising and 25% for falling 1b = 50%

7.6.2.18 MON_CTRL6 Register (Address = 30h) [Reset = 20BBh]

MON_CTRL6 is shown in Table 7-34.

Return to the Summary Table.

Table 7-34 MON_CTRL6 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	RESERVED	R	0h	Reserved
13	ALL_CH	R/W	1h	All channel shutdown enable 0b = Associated faulty half-bridge is shutdown (active pull down) in response to VDS, VGS and OCP_SNS. nFAULT goes low after all three channels have the faults. ENABLE_DRV bit is NOT cleared by the device. For a recovery sequence to re-start PWM, MCU uses CLR_FLT and clears ENABLE_DRV (can be in one SPI command), then set ENABLE_DRV to 1b. 1b = All three half-bridges are shutdown (semi-active pull down) in response to VDS, VGS and OCP_SNS. nFAULT goes low if one or multiple channels have the faults. ENABLE_DRV bit is cleared to 0b by the device.
12-8	RESERVED	R	0h	Reserved
7-4	VDS_LVL_HS	R/W	Bh	VDS overcurrent threshold for high-side MOSFETs
3-0	VDS_LVL_LS	R/W	Bh	VDS overcurrent threshold for low-side MOSFETs. The threshold setting is identical to VDS_LVL_HS