JAJSQ22J september   2011  – may 2023 LMK00301

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Revision History
  6. Device Comparison
  7. Pin Configuration and Functions
  8. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. Parameter Measurement Information
    1. 8.1 Differential Voltage Measurement Terminology
  10. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 VCC and VCCO Power Supplies
    4. 9.4 Device Functional Modes
      1. 9.4.1 Clock Inputs
      2. 9.4.2 Clock Outputs
        1. 9.4.2.1 Reference Output
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Driving the Clock Inputs
        2. 10.2.1.2 Crystal Interface
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Termination and Use of Clock Drivers
          1. 10.2.2.1.1 Termination for DC Coupled Differential Operation
          2. 10.2.2.1.2 Termination for AC Coupled Differential Operation
          3. 10.2.2.1.3 Termination for Single-Ended Operation
      3. 10.2.3 Application Curves
  12. 11Power Supply Recommendations
    1. 11.1 Power Supply Sequencing
    2. 11.2 Current Consumption and Power Dissipation Calculations
      1. 11.2.1 Power Dissipation Example #1: Separate VCC and VCCO Supplies with Unused Outputs
      2. 11.2.2 Power Dissipation Example #2: Worst-Case Dissipation
    3. 11.3 Power Supply Bypassing
      1. 11.3.1 Power Supply Ripple Rejection
    4. 11.4 Thermal Management
  13. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 用語集
  15. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Electrical Characteristics

Unless otherwise specified: Vcc = 3.3 V ± 5%, Vcco = 3.3 V ± 5%, 2.5 V ± 5%, -40°C ≤ TA ≤ 85°C, CLKin driven differentially, input slew rate ≥ 3 V/ns. Typical values represent most likely parametric norms at Vcc = 3.3 V, Vcco = 3.3 V, TA = 25°C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured.(1)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
CURRENT CONSUMPTION(2)
ICC_CORECore Supply Current, All Outputs DisabledCLKinX selected8.510.5mA
OSCin selected1013.5mA
ICC_PECLAdditive Core Supply Current, Per LVPECL Bank Enabled2027mA
ICC_LVDSAdditive Core Supply Current, Per LVDS Bank EnabledLMK003012632.5mA
LMK00301A3138
ICC_HCSLAdditive Core Supply Current, Per HCSL Bank Enabled3542mA
ICC_CMOSAdditive Core Supply Current, LVCMOS Output Enabled3.55.5mA
ICCO_PECLAdditive Output Supply Current, Per LVPECL Bank EnabledIncludes Output Bank Bias and Load Currents,
RT = 50 Ω to Vcco - 2V on all outputs in bank
165197mA
ICCO_LVDSAdditive Output Supply Current, Per LVDS Bank EnabledLMK003013444.5mA
LMK00301A2433.5
ICCO_HCSLAdditive Output Supply Current, Per HCSL Bank EnabledIncludes Output Bank Bias and Load Currents,
RT = 50 Ω on all outputs in bank
Vcco = 3.3 V ± 5%87104mA
Vcco = 2.5 V ± 5%
ICCO_CMOSAdditive Output Supply Current, LVCMOS Output Enabled200 MHz, CL = 5 pFVcco = 3.3 V ± 5%910mA
Vcco = 2.5 V ± 5%78mA
POWER SUPPLY RIPPLE REJECTION (PSRR)
PSRRPECLRipple-Induced
Phase Spur Level(3)
Differential LVPECL Output
100 kHz, 100 mVpp Ripple Injected on Vcco,
Vcco = 2.5 V
156.25 MHz-65dBc
312.5 MHz-63
PSRRHCSLRipple-Induced
Phase Spur Level(3)
Differential HCSL Output
156.25 MHz-76dBc
312.5 MHz-74
PSRRLVDSRipple-Induced
Phase Spur Level(3)
Differential LVDS Output
156.25 MHz-72dBc
312.5 MHz-63
CMOS CONTROL INPUTS (CLKin_SELn, CLKoutX_TYPEn, REFout_EN)
VIHHigh-Level Input Voltage1.6VccV
VILLow-Level Input VoltageGND0.4V
IIHHigh-Level Input CurrentVIH = Vcc, Internal pull-down resistor50µA
IILLow-Level Input CurrentVIL = 0 V, Internal pull-down resistor-50.1µA
CLOCK INPUTS (CLKin0/CLKin0*, CLKin1/CLKin1*)
fCLKinInput Frequency Range(10)Functional up to 3.1 GHz
Output frequency range and timing specified per output type (refer to LVPECL, LVDS, HCSL, LVCMOS output specifications)
DC3.1GHz
VIHDDifferential Input High VoltageCLKin driven differentiallyVccV
VILDDifferential Input Low VoltageGNDV
VIDDifferential Input Voltage Swing(4)0.151.3V
VCMDDifferential Input Common Mode VoltageVID = 150 mV0.25Vcc - 1.2V
VID = 350 mV0.25Vcc - 1.1
VID = 800 mV0.25Vcc - 0.9
VIHSingle-Ended Input High VoltageCLKinX driven single-ended (AC or DC coupled), CLKinX* AC coupled to GND or externally biased within VCM rangeVccV
VILSingle-Ended Input Low VoltageGNDV
VI_SESingle-Ended Input Voltage Swing(15)(17)0.32Vpp
VCMSingle-Ended Input Common Mode Voltage0.25Vcc - 1.2V
ISOMUXMux Isolation, CLKin0 to CLKin1fOFFSET > 50 kHz,
PCLKinX = 0 dBm
fCLKin0 = 100 MHz-84dBc
fCLKin0 = 200 MHz-82
fCLKin0 = 500 MHz-71
fCLKin0 = 1000 MHz-65
CRYSTAL INTERFACE (OSCin, OSCout)
FCLKExternal Clock Frequency Range(10)OSCin driven single-ended, OSCout floating250MHz
FXTALCrystal Frequency RangeFundamental mode crystal
ESR ≤ 200 Ω (10 to 30 MHz)
ESR ≤ 125 Ω (30 to 40 MHz)(5)
1040MHz
CINOSCin Input Capacitance4pF
LVPECL OUTPUTS (CLKoutAn/CLKoutAn*, CLKoutBn/CLKoutBn*)
fCLKout_FSMaximum Output Frequency Full VOD Swing(10)(11)VOD ≥ 600 mV,
RL = 100 Ω differential
Vcco = 3.3 V ± 5%,
RT = 160 Ω to GND
1.01.2GHz
Vcco = 2.5 V ± 5%,
RT = 91 Ω to GND
0.751.0
fCLKout_RSMaximum Output Frequency Reduced VOD Swing(10)(11)VOD ≥ 400 mV,
RL = 100 Ω differential
Vcco = 3.3 V ± 5%,
RT = 160 Ω to GND
1.53.1GHz
Vcco = 2.5 V ± 5%,
RT = 91 Ω to GND
1.52.3
JitterADDAdditive RMS Jitter, Integration Bandwidth
10 kHz to 20 MHz(15)(6)(16)
Vcco = 2.5 V ± 5%:
RT = 91 Ω to GND,
Vcco = 3.3 V ± 5%:
RT = 160 Ω to GND,
RL = 100 Ω differential
CLKin: 100 MHz,
Slew rate ≥ 3 V/ns
7798fs
CLKin: 156.25 MHz,
Slew rate ≥ 3 V/ns
5478
JitterADDAdditive RMS Jitter Integration Bandwidth
1 MHz to 20 MHz(6)
Vcco = 3.3 V,
RT = 160 Ω to GND,
RL = 100 Ω differential
CLKin: 100 MHz,
Slew rate ≥ 3 V/ns
59fs
CLKin: 156.25 MHz, Slew rate ≥ 2.7 V/ns64
CLKin: 625 MHz,
Slew rate ≥ 3 V/ns
30
JitterADDAdditive RMS Jitter with LVPECL clock source from LMK03806(6)(7)Vcco = 3.3 V,
RT = 160 Ω to GND,
RL = 100 Ω differential
CLKin: 156.25 MHz, JSOURCE = 190 fs RMS (10 kHz to 1 MHz)20fs
CLKin: 156.25 MHz, JSOURCE = 195 fs RMS (12 kHz to 20 MHz)51
Noise FloorNoise Floor
fOFFSET ≥ 10 MHz(8)(9)
Vcco = 3.3 V,
RT = 160 Ω to GND,
RL = 100 Ω differential
CLKin: 100 MHz,
Slew rate ≥ 3 V/ns
-162.5dBc/Hz
CLKin: 156.25 MHz, Slew rate ≥ 2.7 V/ns-158.1
CLKin: 625 MHz,
Slew rate ≥ 3 V/ns
-154.4
DUTYDuty Cycle(10)50% input clock duty cycle45%55%
VOHOutput High VoltageTA = 25°C, DC Measurement,
RT = 50 Ω to Vcco - 2 V
Vcco - 1.2Vcco - 0.9Vcco - 0.7V
VOLOutput Low VoltageVcco - 2.0Vcco - 1.75Vcco - 1.5V
VODOutput Voltage Swing(4)6008301000mV
tROutput Rise Time
20% to 80%(15)
RT = 160 Ω to GND, Uniform transmission line up to 10 in. with 50-Ω characteristic impedance,
RL = 100 Ω differential, CL ≤ 5 pF
175300ps
tFOutput Fall Time
80% to 20%(15)
175300ps
LVDS OUTPUTS (CLKoutAn/CLKoutAn*, CLKoutBn/CLKoutBn*)
fCLKout_FSMaximum Output Frequency
Full VOD Swing(10)(11)
VOD ≥ 250 mV,
RL = 100 Ω differential
1.01.6GHz
fCLKout_RSMaximum Output Frequency
Reduced VOD Swing(10)(11)
VOD ≥ 200 mV,
RL = 100 Ω differential
1.52.1GHz
JitterADDAdditive RMS Jitter,
Integration Bandwidth
10 kHz to 20 MHz(15)(6)(16)
RL = 100 Ω differentialCLKin: 100 MHz,
Slew rate ≥ 3 V/ns
94115fs
CLKin: 156.25 MHz,
Slew rate ≥ 3 V/ns
7090
JitterADDAdditive RMS Jitter
Integration Bandwidth
1 MHz to 20 MHz(6)
Vcco = 3.3 V,
RL = 100 Ω differential
CLKin: 100 MHz,
Slew rate ≥ 3 V/ns
89fs
CLKin: 156.25 MHz,
Slew rate ≥ 2.7 V/ns
77
CLKin: 625 MHz,
Slew rate ≥ 3 V/ns
37
Noise FloorNoise Floor
fOFFSET ≥ 10 MHz(8)(9)
Vcco = 3.3 V,
RL = 100 Ω differential
CLKin: 100 MHz,
Slew rate ≥ 3 V/ns
-159.5dBc/Hz
CLKin: 156.25 MHz,
Slew rate ≥ 2.7 V/ns
-157.0
CLKin: 625 MHz,
Slew rate ≥ 3 V/ns
-152.7
DUTYDuty Cycle(10)50% input clock duty cycle45%55%
VODOutput Voltage Swing(4)TA = 25°C, DC Measurement,
RL = 100 Ω differential
250400450mV
ΔVODChange in Magnitude of VOD for Complementary Output States-5050mV
VOSOutput Offset Voltage1.1251.251.375V
ΔVOSChange in Magnitude of VOS for Complementary Output States-3535mV
ISA
ISB
Output Short Circuit Current Single EndedTA = 25°C,
Single ended outputs shorted to GND
-2424mA
ISABOutput Short Circuit Current DifferentialComplementary outputs tied together-1212mA
tROutput Rise Time
20% to 80%(15)
Uniform transmission line up to 10 inches with 50-Ω characteristic impedance,
RL = 100 Ω differential, CL ≤ 5 pF
175300ps
tFOutput Fall Time
80% to 20%(15)
175300ps
HCSL OUTPUTS (CLKoutAn/CLKoutAn*, CLKoutBn/CLKoutBn*)
fCLKoutOutput Frequency Range(10)RL = 50 Ω to GND, CL ≤ 5 pFDC800MHz
JitterADD_PCIeAdditive RMS Phase Jitter for PCIe 6.04PLL BW: 0.5 - 1 MHz; CDR = 10 MHz CLKin: 100 MHz,
Slew rate ≥ 2 V/ns
0.020.025ps
Additive RMS Phase Jitter for PCIe 5.04 PCIe5.0 filter 0.03 0.035
Additive RMS Phase Jitter for PCIe 3.0(10) PCIe Gen 3,
PLL BW = 2–5 MHz,
CDR = 10 MHz
CLKin: 100 MHz,
Slew rate ≥ 0.6 V/ns
0.03 0.15
Additive RMS Phase Jitter for PCIe 4.0(4)PCIe Gen 4,
PLL BW = 2–5 MHz,
CDR = 10 MHz
CLKin: 100 MHz,
Slew rate ≥ 1.8 V/ns
0.030.05
JitterADDAdditive RMS Jitter
Integration Bandwidth
1 MHz to 20 MHz(6)
Vcco = 3.3 V,
RT = 50 Ω to GND
CLKin: 100 MHz,
Slew rate ≥ 3 V/ns
77fs
CLKin: 156.25 MHz,
Slew rate ≥ 2.7 V/ns
86
Noise FloorNoise Floor
fOFFSET ≥ 10 MHz(8)(9)
Vcco = 3.3 V,
RT = 50 Ω to GND
CLKin: 100 MHz,
Slew rate ≥ 3 V/ns
-161.3dBc/Hz
CLKin: 156.25 MHz,
Slew rate ≥ 2.7 V/ns
-156.3
DUTYDuty Cycle(10)50% input clock duty cycleCLKin ≤ 400 MHz45%55%
VOHOutput High VoltageTA = 25°C, DC Measurement,520810920mV
VOLOutput Low Voltage-1500.5150mV
VCROSSAbsolute Crossing Voltage
(10)(12)
RL = 50 Ω to GND, CL ≤ 5 pFCLKin ≤ 400 MHz160350460mV
ΔVCROSSTotal Variation of VCROSS
(10)(12)
140mV
tROutput Rise Time
20% to 80%(15)(12)
250 MHz, Uniform transmission line up to 10 inches with 50-Ω characteristic impedance,
RL = 50 Ω to GND, CL ≤ 5 pF
300500ps
tFOutput Fall Time
80% to 20%(15)(12)
300500ps
LVCMOS OUTPUT (REFout)
fCLKoutOutput Frequency Range(10)CL ≤ 5 pFDC250MHz
JitterADDAdditive RMS Jitter
Integration Bandwidth
1 MHz to 20 MHz(6)
Vcco = 3.3 V, CL ≤ 5 pF100 MHz, Input Slew rate ≥ 3 V/ns95fs
Noise FloorNoise Floor
fOFFSET ≥ 10 MHz(8)(9)
Vcco = 3.3 V, CL ≤ 5 pF100 MHz, Input Slew rate ≥ 3 V/ns-159.3dBc/Hz
DUTYDuty Cycle(10)50% input clock duty cycle45%55%
VOHOutput High Voltage1 mA loadVcco - 0.1V
VOLOutput Low Voltage0.1V
IOHOutput High Current (Source)Vo = Vcco / 2Vcco = 3.3 V28mA
Vcco = 2.5 V20
IOLOutput Low Current (Sink)Vcco = 3.3 V28mA
Vcco = 2.5 V20
tROutput Rise Time
20% to 80%(15)(12)
250 MHz, Uniform transmission line up to 10 inches with 50-Ω characteristic impedance,
RL = 50 Ω to GND, CL ≤ 5 pF
225400ps
tFOutput Fall Time
80% to 20%(15)(12)
225400ps
tENOutput Enable Time(13)CL ≤ 5 pF3cycles
tDISOutput Disable Time(13)3cycles
PROPAGATION DELAY and OUTPUT SKEW
tPD_PECLPropagation Delay
CLKin-to-LVPECL(15)
RT = 160 Ω to GND, RL = 100 Ω differential, CL ≤ 5 pF180360540ps
tPD_LVDSPropagation Delay
CLKin-to-LVDS(15)
RL = 100 Ω differential, CL ≤ 5 pF200400600ps
tPD_HCSLPropagation Delay
CLKin-to-HCSL(15)(12)
RT = 50 Ω to GND, CL ≤ 5 pF295590885ps
tPD_CMOSPropagation Delay
CLKin-to-LVCMOS(15)(12)
CL ≤ 5 pFVcco = 3.3 V90014752300ps
Vcco = 2.5 V100015502700
tSK(O)Output Skew
LVPECL/LVDS/HCSL
(10)(12)(14)
Skew specified between any two CLKouts with the same buffer type. Load conditions per output type are the same as propagation delay specifications.3050ps
tSK(PP)Part-to-Part Output Skew LVPECL/LVDS/HCSL
(15)(12)(14)
80120ps
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured.
See Power Supply Recommendations for more information on current consumption and power dissipation calculations. Characteristics for both LMK00301 and LMK00301A are the same unless specified under the test conditions.
Power supply ripple rejection, or PSRR, is defined as the single-sideband phase spur level (in dBc) modulated onto the clock output when a single-tone sinusoidal signal (ripple) is injected onto the Vcco supply. Assuming no amplitude modulation effects and small index modulation, the peak-to-peak deterministic jitter (DJ) can be calculated using the measured single-sideband phase spur level (PSRR) as follows: DJ (ps pk-pk) = [ (2 * 10(PSRR / 20)) / (π * fCLK) ] * 1E12
See Differential Voltage Measurement Terminology for definition of VID and VOD voltages.
The ESR requirements stated must be met to ensure that the oscillator circuitry has no startup issues. However, lower ESR values for the crystal may be necessary to stay below the maximum power dissipation (drive level) specification of the crystal. Refer to Crystal Interface for crystal drive level considerations.
For the 100 MHz and 156.25 MHz clock input conditions, Additive RMS Jitter (JADD) is calculated using Method #1: JADD = SQRT(JOUT2 - JSOURCE2), where JOUT is the total RMS jitter measured at the output driver and JSOURCE is the RMS jitter of the clock source applied to CLKin. For the 625 MHz clock input condition, Additive RMS Jitter is approximated using Method #2: JADD = SQRT(2*10dBc/10) / (2*π*fCLK), where dBc is the phase noise power of the Output Noise Floor integrated from 1 to 20 MHz bandwidth. The phase noise power can be calculated as: dBc = Noise Floor + 10*log10(20 MHz - 1 MHz). The additive RMS jitter was approximated for 625 MHz using Method #2 because the RMS jitter of the clock source was not sufficiently low enough to allow practical use of Method #1. Refer to the “Noise Floor vs. CLKin Slew Rate” and “RMS Jitter vs. CLKin Slew Rate” plots in Typical Characteristics.
156.25 MHz LVPECL clock source from LMK03806 with 20 MHz crystal reference (crystal part number: ECS-200-20-30BU-DU). Typical JSOURCE = 190 fs RMS (10 kHz to 1 MHz) and 195 fs RMS (12 kHz to 20 MHz). Refer to the LMK03806 data sheet for more information.
The noise floor of the output buffer is measured as the far-out phase noise of the buffer. Typically this offset is ≥ 10 MHz, but for lower frequencies this measurement offset can be as low as 5 MHz due to measurement equipment limitations.
Phase noise floor will degrade as the clock input slew rate is reduced. Compared to a single-ended clock, a differential clock input (LVPECL, LVDS) will be less susceptible to degradation in noise floor at lower slew rates due to its common mode noise rejection. However, it is recommended to use the highest possible input slew rate for differential clocks to achieve optimal noise floor performance at the device outputs.
Specification is ensured by characterization and is not tested in production.
See Typical Characteristics for output operation over frequency.
AC timing parameters for HCSL or CMOS are dependent on output capacitive loading.
Output Enable Time is the number of input clock cycles it takes for the output to be enabled after REFout_EN is pulled high. Similarly, Output Disable Time is the number of input clock cycles it takes for the output to be disabled after REFout_EN is pulled low. The REFout_EN signal should have an edge transition much faster than that of the input clock period for accurate measurement.
Output skew is the propagation delay difference between any two outputs with identical output buffer type and equal loading while operating at the same supply voltage and temperature conditions.
Parameter is specified by design, not tested in production.
100 MHz and 156.25 MHz input source from Rohde & Schwarz SMA100A Low-Noise Signal Generator and Sine-to-Square-wave Conversion block
For clock input frequency ≥ 100 MHz, CLKinX can be driven with single-ended (LVCMOS) input swing up to 3.3 Vpp. For clock input frequency < 100 MHz, the single-ended input swing should be limited to 2 Vpp max to prevent input saturation (refer to Driving the Clock Inputs for interfacing 2.5 V/3.3 V LVCMOS clock input < 100 MHz to CLKinX).