JAJSHQ1A October   2017  – July 2019 LMK04228

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     概略回路図
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 SPI Interface Timing
    7. 7.7 Timing Diagram
  8. 8 Parameter Measurement Information
    1. 8.1 Charge Pump Current Specification Definitions
      1. 8.1.1 Charge Pump Output Current Magnitude Variation vs. Charge Pump Output Voltage
      2. 8.1.2 Charge Pump Sink Current vs. Charge Pump Output Source Current Mismatch
      3. 8.1.3 Charge Pump Output Current Magnitude Variation vs. Ambient Temperature
    2. 8.2 Differential Voltage Measurement Terminology
  9. 9 Detailed Description
    1. 9.1 Overview
      1. 9.1.1 Jitter Cleaning
      2. 9.1.2 JEDEC JESD204B Support
      3. 9.1.3 Three PLL1 Redundant Reference Inputs (CLKin0/CLKin0*, CLKin1/CLKin1*, and CLKin2/CLKin2*)
      4. 9.1.4 VCXO- and Crystal-Buffered Output
      5. 9.1.5 Frequency Holdover
      6. 9.1.6 PLL2 Integrated Loop Filter Poles
      7. 9.1.7 Internal VCOs
      8. 9.1.8 Clock Distribution
        1. 9.1.8.1 Device Clock Divider
        2. 9.1.8.2 SYSREF Clock Divider
        3. 9.1.8.3 Device Clock Delay
        4. 9.1.8.4 SYSREF Delay
        5. 9.1.8.5 Programmable Output Formats
        6. 9.1.8.6 Clock Output Synchronization
      9. 9.1.9 Status Pins
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
      1. 9.3.1 SYNC/SYSREF
      2. 9.3.2 JEDEC JESD204B
        1. 9.3.2.1 How to Enable SYSREF
          1. 9.3.2.1.1 Setup of SYSREF Example
          2. 9.3.2.1.2 SYSREF_CLR
        2. 9.3.2.2 SYSREF Modes
          1. 9.3.2.2.1 SYSREF Pulser
          2. 9.3.2.2.2 Continuous SYSREF
          3. 9.3.2.2.3 SYSREF Request
      3. 9.3.3 Digital Delay
        1. 9.3.3.1 Fixed Digital Delay
          1. 9.3.3.1.1 Fixed Digital Delay Example
      4. 9.3.4 SYSREF to Device Clock Alignment
      5. 9.3.5 Input Clock Switching
        1. 9.3.5.1 Input Clock Switching - Manual Mode
        2. 9.3.5.2 Input Clock Switching - Pin Select Mode
          1. 9.3.5.2.1 Configuring Pin Select Mode
        3. 9.3.5.3 Input Clock Switching - Automatic Mode
          1. 9.3.5.3.1 Starting Active Clock
      6. 9.3.6 Digital Lock Detect
        1. 9.3.6.1 Calculating Digital Lock Detect Frequency Accuracy
      7. 9.3.7 Holdover
        1. 9.3.7.1 Enable Holdover
          1. 9.3.7.1.1 Fixed (Manual) CPout1 Holdover Mode
          2. 9.3.7.1.2 Tracked CPout1 Holdover Mode
        2. 9.3.7.2 During Holdover
        3. 9.3.7.3 Exiting Holdover
        4. 9.3.7.4 Holdover Frequency Accuracy and DAC Performance
        5. 9.3.7.5 Holdover Mode - Automatic Exit of Holdover
    4. 9.4 Programming
      1. 9.4.1 Recommended Programming Sequence
        1. 9.4.1.1 SPI LOCK
        2. 9.4.1.2 SYSREF_CLR
    5. 9.5 Register Maps
      1. 9.5.1 Register Map for Device Programming
      2. 9.5.2 Device Register Descriptions
        1. 9.5.2.1 System Functions
          1. 9.5.2.1.1 RESET, SPI_3WIRE_DIS
          2. 9.5.2.1.2 POWERDOWN
          3. 9.5.2.1.3 ID_DEVICE_TYPE
          4. 9.5.2.1.4 ID_PROD[15:8], ID_PROD
          5. 9.5.2.1.5 ID_MASKREV
          6. 9.5.2.1.6 ID_VNDR[15:8], ID_VNDR
        2. 9.5.2.2 (0x100 - 0x138) Device Clock and SYSREF Clock Output Controls
          1. 9.5.2.2.1 CLKoutX_Y_ODL, CLKoutX_Y_IDL, DCLKoutX_DIV
          2. 9.5.2.2.2 DCLKoutX_DDLY_CNTH, DCLKoutX_DDLY_CNTL
          3. 9.5.2.2.3 DCLKoutX_ADLY, DCLKoutX_ADLY_MUX, DCLKout_MUX
          4. 9.5.2.2.4 DCLKoutX_HS, SDCLKoutY_MUX, SDCLKoutY_DDLY, SDCLKoutY_HS
          5. 9.5.2.2.5 SDCLKoutY_ADLY_EN, SDCLKoutY_ADLY
          6. 9.5.2.2.6 DCLKoutX_DDLY_PD, DCLKout_ADLY_PD, DCLKoutX_Y_PD, SDCLKoutY_DIS_MODE, SDCLKoutY_PD
          7. 9.5.2.2.7 SDCLKoutY_POL, SDCLKoutY_FMT, DCLKoutX_POL, DCLKoutX_FMT
        3. 9.5.2.3 SYSREF, SYNC, and Device Config
          1. 9.5.2.3.1 VCO_MUX, OSCout_FMT
          2. 9.5.2.3.2 SYSREF_CLKin0_MUX, SYSREF_MUX
          3. 9.5.2.3.3 SYSREF_DIV[12:8], SYSREF_DIV[7:0]
          4. 9.5.2.3.4 SYSREF_DDLY[12:8], SYSREF_DDLY[7:0]
          5. 9.5.2.3.5 SYSREF_PULSE_CNT
          6. 9.5.2.3.6 PLL1_PD, VCO_LDO_PD, VCO_PD, OSCin_PD, SYSREF_GBL_PD, SYSREF_PD, SYSREF_DDLY_PD, SYSREF_PLSR_PD
          7. 9.5.2.3.7 SYSREF_CLR, SYNC_1SHOT_EN, SYNC_POL, SYNC_EN, SYNC_PLL2_DLD, SYNC_PLL1_DLD, SYNC_MODE
          8. 9.5.2.3.8 SYNC_DISSYSREF, SYNC_DISX
          9. 9.5.2.3.9 Fixed Register
        4. 9.5.2.4 (0x146 - 0x149) CLKin Control
          1. 9.5.2.4.1 CLKin2_EN, CLKin1_EN, CLKin0_EN, CLKin2_TYPE, CLKin1_TYPE, CLKin0_TYPE
          2. 9.5.2.4.2 CLKin_SEL_POL, CLKin_SEL_MODE, CLKin1_OUT_MUX, CLKin0_OUT_MUX
          3. 9.5.2.4.3 CLKin_SEL0_MUX, CLKin_SEL0_TYPE
          4. 9.5.2.4.4 SDIO_RDBK_TYPE, CLKin_SEL1_MUX, CLKin_SEL1_TYPE
        5. 9.5.2.5 RESET_MUX, RESET_TYPE
        6. 9.5.2.6 (0x14B - 0x152) Holdover
          1. 9.5.2.6.1 LOS_TIMEOUT, LOS_EN, TRACK_EN, HOLDOVER_FORCE, MAN_DAC_EN, MAN_DAC[9:8]
          2. 9.5.2.6.2 MAN_DAC[9:8], MAN_DAC[7:0]
          3. 9.5.2.6.3 DAC_TRIP_LOW
          4. 9.5.2.6.4 DAC_CLK_MULT, DAC_TRIP_HIGH
          5. 9.5.2.6.5 DAC_CLK_CNTR
          6. 9.5.2.6.6 CLKin_OVERRIDE, HOLDOVER_PLL1_DET, HOLDOVER_LOS_DET, HOLDOVER_VTUNE_DET, HOLDOVER_HITLESS_SWITCH, HOLDOVER_EN
          7. 9.5.2.6.7 HOLDOVER_DLD_CNT[13:8], HOLDOVER_DLD_CNT[7:0]
        7. 9.5.2.7 (0x153 - 0x15F) PLL1 Configuration
          1. 9.5.2.7.1 CLKin0_R[9:8], CLKin0_R[7:0]
          2. 9.5.2.7.2 CLKin1_R[9:8], CLKin1_R[7:0]
          3. 9.5.2.7.3 CLKin2_R[9:8], CLKin2_R[7:0]
          4. 9.5.2.7.4 PLL1_N
          5. 9.5.2.7.5 PLL1_WND_SIZE, PLL1_CP_TRI, PLL1_CP_POL, PLL1_CP_GAIN
          6. 9.5.2.7.6 PLL1_DLD_CNT[13:8], PLL1_DLD_CNT[7:0]
          7. 9.5.2.7.7 PLL1_LD_MUX, PLL1_LD_TYPE
        8. 9.5.2.8 (0x160 - 0x16E) PLL2 Configuration
          1. 9.5.2.8.1 PLL2_R[4:0]
          2. 9.5.2.8.2 PLL2_P, OSCin_FREQ, PLL2_XTAL_EN, PLL2_REF_2X_EN
          3. 9.5.2.8.3 PLL2_FCAL_DIS
          4. 9.5.2.8.4 PLL2_N
          5. 9.5.2.8.5 PLL2_WND_SIZE, PLL2_CP_GAIN, PLL2_CP_POL, PLL2_CP_TRI
          6. 9.5.2.8.6 SYSREF_REQ_EN, PLL2_DLD_CNT
          7. 9.5.2.8.7 PLL2_LF_R4, PLL2_LF_R3
          8. 9.5.2.8.8 PLL2_LF_C4, PLL2_LF_C3
          9. 9.5.2.8.9 PLL2_LD_MUX, PLL2_LD_TYPE
        9. 9.5.2.9 (0x16F - 0x1FFF) Misc Registers
          1. 9.5.2.9.1  Fixed Register
          2. 9.5.2.9.2  Fixed Register
          3. 9.5.2.9.3  PLL2_PRE_PD, PLL2_PD
          4. 9.5.2.9.4  OPT_REG_1
          5. 9.5.2.9.5  OPT_REG_2
          6. 9.5.2.9.6  RB_PLL1_LD_LOST, RB_PLL1_LD, CLR_PLL1_LD_LOST
          7. 9.5.2.9.7  RB_PLL2_LD_LOST, RB_PLL2_LD, CLR_PLL2_LD_LOST
          8. 9.5.2.9.8  RB_DAC_VALUE(MSB), RB_CLKinX_SEL, RB_CLKinX_LOS
          9. 9.5.2.9.9  RB_DAC_VALUE
          10. 9.5.2.9.10 RB_HOLDOVER
          11. 9.5.2.9.11 SPI_LOCK
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Digital Lock Detect Frequency Accuracy
        1. 10.1.1.1 Minimum Lock Time Calculation Example
      2. 10.1.2 Driving CLKin AND OSCin Inputs
        1. 10.1.2.1 Driving CLKin PINS With a Differential Source
        2. 10.1.2.2 Driving CLKin Pins With a Single-Ended Source
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Device Programming
    3. 10.3 Do's and Don'ts
      1. 10.3.1 Pin Connection Recommendations
  11. 11Power Supply Recommendations
    1. 11.1 Current Consumption / Power Dissipation Calculations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Thermal Management
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 TICS Pro
    2. 13.2 コミュニティ・リソース
    3. 13.3 商標
    4. 13.4 静電気放電に関する注意事項
    5. 13.5 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.4.1 Recommended Programming Sequence

Registers are programmed in numeric order with 0x000 being the first and 0x1FFF being the last register programmed. TI recommends the following programming sequence:

  1. Program register 0x000 with RESET = 1.
  2. Program registers in ascending order from 0x000 to 0x165. Unused or unchanged registers can be skipped, and will remain at default POR values.
  3. Program register 0x171 to 0xAA and 0x172 to 0x02.
  4. Program registers 0x17C and 0x17D.
  5. Program registers 0x166 to 0x1FFF.

Program register 0x17C (OPT_REG_1) and 0x17D (OPT_REG_2) before programming PLL2 in registers: 0x166, 0x167, and 0x168 to optimize VCO1 phase noise performance over temperature.