9.5.1 Register Map for Device Programming
Table 6 provides the register map for device programming. Any register can be read from the same data address it is written to.
Table 6. LMK04228 Register Map
ADDRESS |
DATA |
[20:8] |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
0x000 |
RESET |
0 |
0 |
SPI_3WIRE
_DIS |
0 |
0 |
0 |
0 |
0x002 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
POWER
DOWN |
0x003 |
ID_DEVICE_TYPE |
0x004 |
ID_PROD[15:8] |
0x005 |
ID_PROD[7:0] |
0x006 |
ID_MASKREV |
0x00C |
ID_VNDR[15:8] |
0x00D |
ID_VNDR[7:0] |
0x100 |
0 |
CLKout0_1
_ODL |
CLKout0_1
_IDL |
DCLKout0_DIV |
0x101 |
DCLKout0_DDLY_CNTH |
DCLKout0_DDLY_CNTL |
0x103 |
DCLKout0_ADLY |
DCLKout0_
ADLY_MUX |
DCLKout0_MUX |
0x104 |
0 |
DCLKout0
_HS |
SDCLKout1
_MUX |
SDCLKout1_DDLY |
SDCLKout1
_HS |
0x105 |
0 |
0 |
0 |
SDCLKout1_
ADLY_EN |
SDCLKout1_ADLY |
0x106 |
DCLKout0
_ DDLY_PD |
1 |
1 |
DCLKout0
_ADLY _PD |
CLKout0_1
_PD |
SDCLKout1_DIS_MODE |
SDCLKout1
_PD |
0x107 |
SDCLKout1
_POL |
CLKout1_FMT |
DCLKout0
_POL |
CLKout0_FMT |
0x108 |
0 |
CLKout2_3
_ODL |
CLKout2_3
_IDL |
DCLKout2_DIV |
0x109 |
DCLKout2_DDLY_CNTH |
DCLKout2_DDLY_CNTL |
0x10B |
DCLKout2_ADLY |
DCLKout2_
ADLY_MUX |
DCLKout2_MUX |
0x10C |
0 |
DCLKout2
_HS |
SDCLKout3
_MUX |
SDCLKout3_DDLY |
SDCLKout3
_HS |
0x10D |
0 |
0 |
0 |
SDCLKout3
_ ADLY_EN |
SDCLKout3_ADLY |
0x10E |
DCLKout2
_ DDLY_PD |
1 |
1 |
DCLKout2
_ADLY _PD |
CLKout2_3
_PD |
SDCLKout3_DIS_MODE |
SDCLKout3
_PD |
0x10F |
SDCLKout3
_POL |
CLKout3_FMT |
DCLKout2
_POL |
CLKout2_FMT |
0x110 |
0 |
CLKout4_5
_ODL |
CLKout4_5
_IDL |
DCLKout4_DIV |
0x111 |
DCLKout4_DDLY_CNTH |
DCLKout4_DDLY_CNTL |
0x113 |
DCLKout4_ADLY |
DCLKout4_
ADLY_MUX |
DCLKout4_MUX |
0x114 |
0 |
DCLKout4
_HS |
SDCLKout5
_MUX |
SDCLKout5_DDLY |
SDCLKout5
_HS |
0x115 |
0 |
0 |
0 |
SDCLKout5
_ ADLY_EN |
SDCLKout5_ADLY |
0x116 |
DCLKout4
_ DDLY_PD |
1 |
1 |
DCLKout4
_ADLY _PD |
CLKout4_5
_PD |
SDCLKout5_DIS_MODE |
SDCLKout5
_PD |
0x117 |
SDCLKout5
_POL |
CLKout5_FMT |
DCLKout4
_POL |
CLKout4_FMT |
0x118 |
0 |
CLKout6_7
_ODL |
CLKout6_7
_IDL |
DCLKout6_DIV |
0x119 |
DCLKout6_DDLY_CNTH |
DCLKout6_DDLY_CNTL |
0x11B |
DCLKout6_ADLY |
DCLKout6_
ADLY_MUX |
DCLKout6_MUX |
0x11C |
0 |
DCLKout6
_HS |
SDCLKout7
_MUX |
SDCLKout7_DDLY |
SDCLKout7
_HS |
0x11D |
0 |
0 |
0 |
SDCLKout7
_ ADLY_EN |
SDCLKout7_ADLY |
0x11E |
DCLKout6
_ DDLY_PD |
1 |
1 |
DCLKout6
_ADLY _PD |
CLKout6_7
_PD |
SDCLKout7_DIS_MODE |
SDCLKout7
_PD |
0x11F |
SDCLKout7
_POL |
CLKout7
_FMT |
DCLKout6
_POL |
CLKout6_FMT |
0x120 |
0 |
CLKout8_9
_ODL |
CLKout8_9
_IDL |
DCLKout8_DIV |
0x121 |
DCLKout8_DDLY_CNTH |
DCLKout8_DDLY_CNTL |
0x123 |
DCLKout8_ADLY |
DCLKout8
_ ADLY_MUX |
DCLKout8_MUX |
0x124 |
0 |
DCLKout8
_HS |
SDCLKout9
_MUX |
SDCLKout9_DDLY |
SDCLKout9
_HS |
0x125 |
0 |
0 |
0 |
SDCLKout9
_ ADLY_EN |
SDCLKout9_ADLY |
0x126 |
DCLKout8
_ DDLY_PD |
1 |
1 |
DCLKout8
_ADLY _PD |
CLKout8_9
_PD |
SDCLKout9_DIS_MODE |
SDCLKout9
_PD |
0x127 |
SDCLKout9
_POL |
CLKout9_FMT |
DCLKout8
_POL |
CLKout8_FMT |
0x128 |
0 |
CLKout10
_11 _ODL |
CLKout10
_11_IDL |
DCLKout10_DIV |
0x129 |
DCLKout10_DDLY_CNTH |
DCLKout10_DDLY_CNTL |
0x12B |
DCLKout10_ADLY |
DCLKout10
_ ADLY_MUX |
DCLKout10_MUX |
0x12C |
0 |
DCLKout10
_HS |
SDCLKout11
_MUX |
SDCLKout11_DDLY |
SDCLKout11
_HS |
0x12D |
0 |
0 |
0 |
SDCKLout11
_ ADLY_EN |
SDCLKout11_ADLY |
0x12E |
DCLKout10
_ DDLY_PD |
1 |
1 |
DCLKout10
_ ADLY_PD |
CLKout10
_11_PD |
SDCLKout11_DIS_MODE |
SDCLKout11
_PD |
0x12F |
SDCLKout11
_POL |
CLKout11_FMT |
DCLKout10
_POL |
CLKout10_FMT |
0x130 |
0 |
CLKout12
_13 _ODL |
CLKout12
_13_IDL |
DCLKout12_DIV |
0x131 |
DCLKout12_DDLY_CNTH |
DCLKout12_DDLY_CNTL |
0x133 |
DCLKout12_ADLY |
DCLKout12_
ADLY_MUX |
DCLKout12_MUX |
0x134 |
0 |
DCLKout12
_HS |
SDCLKout13
_MUX |
SDCLKout13_DDLY |
SDCLKout13
_HS |
0x135 |
0 |
0 |
0 |
SDCLKout13
_ ADLY_EN |
SDCLKout13_ADLY |
0x136 |
DCLKout12
_ DDLY_PD |
1 |
1 |
DCLKout12
_ ADLY_PD |
CLKout12
_13_PD |
SDCLKout13_DIS_MODE |
SDCLKout13
_PD |
0x137 |
SDCLKout13
_POL |
CLKout13_FMT |
DCLKout12
_POL |
CLKout12_FMT |
0x138 |
0 |
VCO_MUX |
0 |
OSCout_FMT |
0x139 |
0 |
0 |
0 |
0 |
0 |
SYSREF_
CLKin0_MUX |
SYSREF_MUX |
0x13A |
0 |
0 |
0 |
SYSREF_DIV[12:8] |
0x13B |
SYSREF_DIV[7:0] |
0x13C |
0 |
0 |
0 |
SYSREF_DDLY[12:8] |
0x13D |
SYSREF_DDLY[7:0] |
0x13E |
0 |
0 |
0 |
0 |
0 |
0 |
SYSREF_PULSE_CNT |
0x140 |
PLL1_PD |
VCO_LDO_PD |
VCO_PD |
OSCin_PD |
SYSREF_GBL
_PD |
SYSREF_PD |
SYSREF
_DDLY_PD |
SYSREF
_PLSR_PD |
0x143 |
SYSREF_DDLY
_CLR |
SYNC_1SHOT
_EN |
SYNC_POL |
SYNC_EN |
SYNC_PLL2
_DLD |
SYNC_PLL1
_DLD |
SYNC_MODE |
0x144 |
SYNC
_DISSYSREF |
SYNC_DIS12 |
SYNC_DIS10 |
SYNC_DIS8 |
SYNC_DIS6 |
SYNC_DIS4 |
SYNC_DIS2 |
SYNC_DIS0 |
0x145 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
0x146 |
0 |
0 |
CLKin2_EN |
CLKin1_EN |
CLKin0_EN |
CLKin2_TYPE |
CLKin1_TYPE |
CLKin0_TYPE |
0x147 |
CLKin_SEL
_POL |
CLKin_SEL_MODE |
CLKin1_OUT_MUX |
CLKin0_OUT_MUX |
0x148 |
0 |
0 |
CLKin_SEL0_MUX |
CLKin_SEL0_TYPE |
0x149 |
0 |
SDIO_RDBK
_TYPE |
CLKin_SEL1_MUX |
CLKin_SEL1_TYPE |
0x14A |
0 |
0 |
RESET_MUX |
RESET_TYPE |
0x14B |
LOS_TIMEOUT |
LOS_EN |
TRACK_EN |
HOLDOVER
_ FORCE |
MAN_DAC
_EN |
MAN_DAC[9:8] |
0x14C |
MAN_DAC[7:0] |
0x14D |
0 |
0 |
DAC_TRIP_LOW |
0x14E |
DAC_CLK_MULT |
DAC_TRIP_HIGH |
0x14F |
DAC_CLK_CNTR |
0x150 |
0 |
CLKin
_OVERRIDE |
0 |
HOLDOVER
_ PLL1_DET |
HOLDOVER
_LOS _DET |
HOLDOVER
_VTUNE_DET |
HOLDOVER
_HITLESS
_SWITCH |
HOLDOVER
_EN |
0x151 |
0 |
0 |
HOLDOVER_DLD_CNT[13:8] |
0x152 |
HOLDOVER_DLD_CNT[7:0] |
0x153 |
0 |
0 |
0 |
0 |
0 |
0 |
CLKin0_R[9:8] |
0x154 |
CLKin0_R[7:0] |
0x155 |
0 |
0 |
0 |
0 |
0 |
0 |
CLKin1_R[9:8] |
0x156 |
CLKin1_R[7:0] |
0x157 |
0 |
0 |
0 |
0 |
0 |
0 |
CLKin2_R[9:8] |
0x158 |
CLKin2_R[7:0] |
0x159 |
0 |
0 |
0 |
0 |
PLL1_N[11:8] |
0x15A |
PLL1_N[7:0] |
0x15B |
PLL1_WND_SIZE |
PLL1
_CP_TRI |
PLL1
_CP_POL |
PLL1_CP_GAIN |
0x15C |
0 |
0 |
PLL1_DLD_CNT[13:8] |
0x15D |
PLL1_DLD_CNT[7:0] |
0x15F |
PLL1_LD_MUX |
PLL1_LD_TYPE |
0x161 |
0 |
0 |
0 |
PLL2_R[4:0] |
0x162 |
PLL2_P |
OSCin_FREQ |
PLL2
_XTAL_EN |
PLL2
_REF_2X_EN |
0x166 |
0 |
0 |
0 |
0 |
0 |
PLL2_FCAL
_DIS |
0 |
0 |
0x168 |
PLL2_N[7:0] |
0x169 |
0 |
PLL2_WND_SIZE |
PLL2_CP_GAIN |
PLL2
_CP_POL |
PLL
2_CP_TRI |
1 |
0x16A |
0 |
SYSREF_REQ_EN |
PLL2_DLD_CNT[15:8] |
0x16B |
PLL2_DLD_CNT[7:0] |
0x16C |
0 |
0 |
PLL2_LF_R4 |
PLL2_LF_R3 |
0x16D |
PLL2_LF_C4 |
PLL2_LF_C3 |
0x16E |
PLL2_LD_MUX |
PLL2_LD_TYPE |
0x171 |
1 |
0 |
1 |
0 |
1 |
0 |
1 |
0 |
0x172 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0x173 |
0 |
PLL2_PRE_PD |
PLL2_PD |
0 |
0 |
0 |
0 |
0 |
0x17C |
OPT_REG_1 |
0x17D |
OPT_REG_2 |
0x182 |
0 |
0 |
0 |
0 |
0 |
RB_PLL1_
LD_LOST |
RB_PLL1_LD |
CLR_PLL1_
LD_LOST |
0x183 |
0 |
0 |
0 |
0 |
0 |
RB_PLL2_
LD_LOST |
RB_PLL2_LD |
CLR_PLL2_
LD_LOST |
0x184 |
RB_DAC_VALUE[9:8] |
RB_CLKin2_
SEL |
RB_CLKin1_
SEL |
RB_CLKin0_
SEL |
X |
RB_CLKin1_
LOS |
RB_CLKin0_
LOS |
0x185 |
RB_DAC_VALUE[7:0] |
0x188 |
0 |
0 |
0 |
RB_
HOLDOVER |
X |
X |
X |
X |
0x1FFD |
SPI_LOCK[23:16] |
0x1FFE |
SPI_LOCK[15:8] |
0x1FFF |
SPI_LOCK[7:0] |