JAJSRJ1A June   2011  – February 2024 OPA564-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Adjustable Current Limit
        1. 7.3.1.1 Setting the Current Limit
      2. 7.3.2 Enable and Shutdown (E/S) Pin
      3. 7.3.3 Input Protection
      4. 7.3.4 Output Shutdown
      5. 7.3.5 Microcontroller Compatibility
      6. 7.3.6 Current Limit Flag
      7. 7.3.7 Thermal Protection
      8. 7.3.8 Junction Temperature Measurement Using TSENSE
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Basic Configuration
      2. 8.1.2 Output-Stage Compensation
      3. 8.1.3 Output Protection
      4. 8.1.4 Power Dissipation and Safe Operating Area
    2. 8.2 Typical Applications
      1. 8.2.1 Improved Howland Current Pump
      2. 8.2.2 Programmable Power Supply
      3. 8.2.3 Powerline Communication
      4. 8.2.4 Motor-Drive Circuit
      5. 8.2.5 DC Motor-Speed Controller (Without Tachometer)
      6. 8.2.6 Generating VDIG
      7. 8.2.7 Temperature Measurement
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Thermally Enhanced PowerPAD™ Integrated Circuit Package
          1. 8.4.1.1.1 Bottom-Side Thermal Pad Assembly Process
  10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

at TCASE = +25°C, VS = ±12V, RLOAD = 20kΩ to GND, RSET = 7.5kΩ, and E/S pin enabled (unless otherwise noted)
PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage VCM = 0V ±2 ±20 mV
dVOS/dT vs temperature TA = –40°C to +125°C ±10 μV/°C
PSRR vs power supply VCM = 0V, VS = ±3.5V to ±13V 10 150 μV/V
INPUT BIAS CURRENT
IB Input bias current(1) VCM = 0V 10 100 pA
vs temperature TA = –40°C to +125°C See Figure 6-10
IOS Input offset current(1) 10 100 pA
NOISE
en Input voltage noise density f = 1kHz 102.8 nV/√ Hz
f = 10kHz 20 nV/√ Hz
f = 100kHz 8 nV/√ Hz
In Input current noise f = 1kHz 4 fA/√ Hz
INPUT VOLTAGE RANGE
VCM Common-mode voltage Linear operation (V–) (V+) – 3 V
CMRR Common-mode rejection ratio VCM = (V–) to (V+) – 3V 70 80 dB
VCM = (V–) to (V+) – 3V, TA = –40°C to +125°C See Figure 6-9
INPUT IMPEDANCE
Input impedance Differential 1012 || 16 Ω || pF
Common-mode 1012 || 9 Ω || pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain VOUT = 20VPP, RLOAD = 1kΩ 80 108 dB
VOUT = 20VPP, RLOAD = 10Ω 93 dB
FREQUENCY RESPONSE
GBW Gain-bandwidth product(1) RLOAD = 5Ω 17 MHz
SR Slew rate G = 1, 10V step 40 V/μs
Full power bandwidth G = +2, VOUT = 10VPP 1.3 MHz
Settling time G = +1, 10V step, CLOAD = 100pF ±0.1% 0.6 μs
±0.01% 0.8 μs
THD+N Total harmonic distortion + noise f = 1kHz, RLOAD = 5Ω, G = +1, VOUT = 5VP 0.003 %
OUTPUT
VOUT Voltage output Positive IOUT = 0.5A (V+) – 1 (V+) – 0.4 V
IOUT = 1.5A (V+) – 2 (V+) – 1.5 V
Negative IOUT = –0.5A (V–) + 1 (V–) + 0.3 V
IOUT = –1.5A (V–) + 2 (V–) + 1.1 V
IOUT Maximum continuous current, dc 1.5(2) A
RO Output impedance, closed loop f = 100kHz 10 Ω
ZO Output impedance, open loop G = +2, f = 100kHz See Figure 6-24
Output current limit range(3) ±0.4 to ±1.9 A
ILIM Current limit equation I L I M ≅ 20 k × 1.2 V 5 k Ω + R S E T (4)(5) A
Solved for RSET (current limit) RSET ≅ (24kΩ / ILIM) – 5kΩ Ω
Current limit accuracy ILIM = 1.5A 10 %
Current limit overshoot(1)(6) VIN = 5V pulse (200ns tr), G = +2 50 %
Output impedance(7) Output shutdown 6 || 120 GΩ || pF
CLOAD Capacitive load drive See Figure 6-6
DIGITAL CONTROL
VE/ S high (output enabled) VDIG = 3.3V to 5.5V referenced to V– E/S pin open or forced high (V–) + 2 (V–) + VDIG V
VE/ S Low (output shut down) E/S pin forced low (V–) (V–) + 0.8 V
IE/S high (output enabled) E/S pin indicates high 10 μA
IE/S low (output shut down) E/S pin indicates low 1 μA
Output shutdown time 1 μs
Output enable time 3 μs
Current limit flag output Normal operation, sinking 10μA V– (V–) + 0.8 V
Current-limited operation, sourcing 20μA (V–) + 2 VDIG V
THERMAL SHUTDOWN
Normal operation Sinking 200μA V– (V–) + 0.8 V
Thermal shutdown(8) Sourcing 200μA (V–) + 2 VDIG V
Junction temperature at shutdown(9) 140 to 157 °C
Hysteresis(9) 15 to 19 °C
TSENSE
η Diode ideality factor 1.033
POWER SUPPLY(10)
IQ Quiescent current(4) IOUT = 0A 39 50 mA
IOUT = 0A, TA = –40°C to 125°C 50 mA
IQSD Quiescent current in shutdown mode 5 mA
IDIG Digital quiescent current VDIG = 5V 43 100 μA
(1) See Section 6.6.
(2) Under safe operating conditions; see also Section 8.1.4.
(3) Minimum current limit is 0.4A; see also Section 7.3.1.
(4) Quiescent current increases when the current limit is increased (see also Figure 6-33).
(5) RSET (current limit) ranges from 55kΩ (IOUT = 400mA) to 10kΩ (IOUT = 1.6A typical); see also Section 7.3.1.
(6) Transient load transition time must be ≥ 200ns.
(7) See also Section 7.3.2.
(8) When sourcing, the VDIG supply must be able to supply the current.
(9) Characterized, but not production tested.
(10) Power-supply sequencing requirements must be observed. See Section 8.3 for more information.