JAJSSB8 November   2023 TDP2004

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 DC Electrical Characteristics
    6. 5.6 High Speed Electrical Characteristics
    7. 5.7 SMBUS/I2C Timing Characteristics
    8. 5.8 Typical Characteristics
    9. 5.9 Typical Jitter Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Linear Equalization
      2. 6.3.2 Flat-Gain
    4. 6.4 Device Functional Modes
      1. 6.4.1 Active Mode
      2. 6.4.2 Standby Mode
    5. 6.5 Programming
      1. 6.5.1 Pin mode
        1. 6.5.1.1 Five-Level Control Inputs
      2. 6.5.2 SMBUS/I2C Register Control Interface
        1. 6.5.2.1 Shared Registers
        2. 6.5.2.2 Channel Registers
      3. 6.5.3 SMBus/I 2 C Primary Mode Configuration (EEPROM Self Load)
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 DP 2.1 Mainlink Signal Conditioning
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 Pin Configuration and Functions

GUID-20231103-SS0I-0K2R-LPWZ-NTMKQ54NXVJP-low.svg Figure 4-1 RNQ Package,40-Pin WQFN(Top View)
Table 4-1 Pin Functions
PINTYPE(1)DESCRIPTION
NAMENO.
DONEn7O, 3.3 V open drainIn SMBus/I2C Primary mode:
Indicates the completion of a valid EEPROM register load operation. External pullup resistor such as 4.7 kΩ required for operation.
High: External EEPROM load failed or incomplete
Low: External EEPROM load successful and complete
In SMBus/I2C Secondary/Pin mode:
This output is High-Z. The pin can be left floating.
MODE25I, 5-levelSets device control configuration modes. 5-level IO pin as provided in Table 6-3. The pin can be exercised at device power up or in normal operation mode.
L0: Pin mode – device control configuration is done solely by strap pins.
L1: SMBus/I2C Primary mode – device control configuration is read from external EEPROM. When the TDP2004 has finished reading from the EEPROM successfully, it will drive the DONEn pin LOW. SMBus/I2C secondary operation is available in this mode before, during or after EEPROM reading. Note: during EEPROM reading if the external SMBus/I2C primary wants to access TDP2004 registers it must support arbitration.
L2: SMBus/I2C Secondary mode – device control configuration is done by an external controller with SMBus/I2C primary.
L3 and L4 (Float): RESERVED – TI internal test modes.
EQ0 / ADDR023I, 5-levelIn Pin mode:
Sets receiver linear equalization (CTLE) boost for channels 0-3 as provided in Table 6-1. These pins are sampled at device power-up only.
In SMBus/I2C mode:
Sets SMBus / I2C secondary address as provided in Table 6-4. These pins are sampled at device power-up only.
EQ1 / ADDR124I, 5-level
GAIN / SDA27I, 5-level / I/O, 3.3 V LVCMOS, open drainIn Pin mode:
Flat gain (DC and AC) from the input to the output of the device for channels 0-3. The pin is sampled at device power-up only.
In SMBus/I2C mode:
3.3 V SMBus/I2C data. External 1 kΩ to 5 kΩ pullup resistor is required as per SMBus / I2C interface standard.
GND1, 8, 11, 18, 21, 28, 31, 38, EPPGround reference for the device.
EP: the Exposed Pad at the bottom of the QFN package. It is used as the GND return for the device. The EP should be connected to one or more ground planes through the low resistance path. A via array provides a low impedance path to GND. The EP also improves thermal dissipation.
PD6I, 3.3 V LVCMOS2-level logic controlling the operating state of the redriver. Active in all device control modes. The pin has internal 1-MΩ weak pull-down resistor.
High: power down for channels 0-3
Low: power up, normal operation for channels 0-3
READ_EN_N22I, 3.3 V LVCMOSIn SMBus/I2C Primary mode:
After device power up, when the pin is low, it initiates the SMBus / I2C Primary mode EEPROM read function. When EEPROM read is complete (indicated by assertion of DONEn low), this pin can be held low for normal device operation. During the EEPROM load process the device’s signal path is disabled.
In SMBus/I2C Secondary and Pin modes:
In these modes the pin is not used. The pin can be left floating. The pin has internal 1-MΩ weak pull-down resistor.
RSVD2—Reserved use for TI. The pin must be left floating (NC).
TEST / SCL26I, 5-level / I/O, 3.3 V LVCMOS, open drainIn Pin mode:
TI test mode. External 1 kΩ pull down resistor must be installed.
In SMBus/I2C mode:
3.3V SMBus/I2C clock. External 1 kΩ to 5 kΩ pullup resistor is required as per SMBus / I2C interface standard.
RX0N30IInverting differential inputs to the equalizer. Integrated 50 Ω termination resistor from the pin to internal CM bias voltage. Channel 0.
RX0P29INon-inverting differential inputs to the equalizer. Integrated 50 Ω termination resistor from the pin to internal CM bias voltage. Channel 0.
RX1N33IInverting differential inputs to the equalizer. Integrated 50 Ω termination resistor from the pin to internal CM bias voltage. Channel 1.
RX1P32INon-inverting differential inputs to the equalizer. Integrated 50 Ω termination resistor from the pin to internal CM bias voltage. Channel 1.
RX2N37IInverting differential inputs to the equalizer. Integrated 50 Ω termination resistor from the pin to internal CM bias voltage. Channel 2.
RX2P36INon-inverting differential inputs to the equalizer. Integrated 50 Ω termination resistor from the pin to internal CM bias voltage. Channel 2.
RX3N40IInverting differential inputs to the equalizer. Integrated 50 Ω termination resistor from the pin to internal CM bias voltage. Channel 3.
RX3P39INon-inverting differential inputs to the equalizer. Integrated 50 Ω termination resistor from the pin to internal CM bias voltage. Channel 3.
TX0N19OInverting pin for 100 Ω differential driver output. Channel 0.
TX0P20ONon-inverting pin for 100 Ω differential driver output. Channel 0.
TX1N16OInverting pin for 100 Ω differential driver output. Channel 1.
TX1P17ONon-inverting pin for 100 Ω differential driver output. Channel 1.
TX2N12OInverting pin for 100 Ω differential driver output. Channel 2.
TX2P13ONon-inverting pin for 100 Ω differential driver output. Channel 2.
TX3N9OInverting pin for 100 Ω differential driver output. Channel 3.
TX3P10ONon-inverting pin for 100 Ω differential driver output. Channel 3.
VCC14, 15, 34, 35PPower supply pins. VCC = 3.3 V ±10%. The VCC pins on this device should be connected through a low-resistance path to the board VCC plane. Install a decoupling capacitor to GND near each VCC pin.
(1) I = input, O = output, P = power