JAJSSB8A November   2023  – April 2024 TDP2004

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 DC Electrical Characteristics
    6. 5.6 High Speed Electrical Characteristics
    7. 5.7 SMBUS/I2C Timing Characteristics
    8. 5.8 Typical Characteristics
    9. 5.9 Typical Jitter Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Linear Equalization
      2. 6.3.2 Flat-Gain
    4. 6.4 Device Functional Modes
      1. 6.4.1 Active Mode
      2. 6.4.2 Standby Mode
    5. 6.5 Programming
      1. 6.5.1 Pin mode
        1. 6.5.1.1 Five-Level Control Inputs
      2. 6.5.2 SMBUS/I2C Register Control Interface
        1. 6.5.2.1 Shared Registers
        2. 6.5.2.2 Channel Registers
      3. 6.5.3 SMBus/I 2 C Primary Mode Configuration (EEPROM Self Load)
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 DP 2.1 Mainlink Signal Conditioning
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RNQ|40
サーマルパッド・メカニカル・データ
発注情報

5.7 SMBUS/I2C Timing Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Secondary Mode
tSP Pulse width of spikes which must be
suppressed by the input filter		 50 ns
tHD-STA Hold time (repeated) START condition.
After this period, the first clock pulse is
generated		 0.6 µs
tLOW LOW period of the SCL clock 1.3 µs
THIGH HIGH period of the SCL clock 0.6 µs
tSU-STA Setup time for a repeated START
condition		 0.6 µs
tHD-DAT Data hold time 0 µs
TSU-DAT Data setup time 0.1 µs
tr Rise time of both SDA and SCL signals Pullup resistor = 4.7kΩ, Cb = 10pF 120 ns
tf Fall time of both SDA and SCL signals Pullup resistor = 4.7kΩ, Cb = 10pF 2 ns
tSU-STO Setup time for STOP condition 0.6 µs
tBUF Bus free time between a STOP and
START condition		 1.3 µs
tVD-DAT Data valid time 0.9 µs
tVD-ACK Data valid acknowledge time 0.9 µs
Cb Capacitive load for each bus line 400 pF
Primary Mode
fSCL-M SCL clock frequency 303 kHz
tLOW-M SCL low period 1.90 µs
THIGH-M SCL high period 1.40 µs
tSU-STA-M Setup time for a repeated START
condition		 2 µs
tHD-STA-M Hold time (repeated) START condition.
After this period, the first clock pulse is
generated		 1.5 µs
TSU-DAT-M Data setup time 1.4 µs
tHD-DAT-M Data hold time 0.5 µs
tR-M Rise time of both SDA and SCL signals Pullup resistor = 4.7kΩ, Cb = 10pF 120 ns
TF-M Fall time of both SDA and SCL signals Pullup resistor = 4.7kΩ, Cb = 10pF 2 ns
tSU-STO-M Stop condition setup time 1.5 µs
EEPROM Timing
TEEPROM EEPROM configuration load time Time to assert DONEn after READ_EN_N has been asserted. 7.5 ms
TPOR Time to first SMBus access Power supply stable after initial ramp. Includes initial power-on reset time. 50 ms